RE: 8360E - PCI / DTC Blob Setup

On Feb 2, 2007, at 7:36 AM, Russell McGuire wrote:

quoted

Well I am getting smarter on this:

I have read through the PCI Bridge Specs and found another issue
that might
have been causing a problem with the IDSEL lines. Unless you are
interested
I'll forgo that explanation and just go with fact that I have
changed the
IDSEL mappings to be legal when they are issued from the 83xx.

I have changed the IDSELs to be as follows, does this look correct?

Not sure, I'm a little confused as to how exactly things are wired on
your board.  It would seem like you have 2 P2P bridges connected to
the processor.  Behind one bridge is 2 slots and behind the second is
1 slot?

Absolutely correct, I probably should send a picture. :-) But yes, the CPU
host bridge is directly connected to a DUAL P2P bridge chip. There are no
SLOTS on BUS 0. The P2P then provides BUS 1 and BUS 2. I did this in the
design to allow slower 33Mhz cards to operate in the system without slowing
down the 66Mhz cards <i.e. a sound card or USB card, but still being able to
run a VGA card or video capture card at high speed>.

BUS 1 has two slots, and BUS 2 has one slot, for a total of three.

I would be more than happy to send a 2 page PDF file of the schematic. This
design obviously hasn't been proofed yet. Though it 'seems' to almost work.

-Russ