Thread (6 messages) 6 messages, 3 authors, 2006-12-28

Re: Chenging 2 bits in MSR in ppc6xx_idle() with 1 command?

From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Date: 2006-12-27 21:15:25

Hm, wouldn't it just work? In ppc6xx_idle() the _TLF_NAPPING bit is set. 
If as a result of mtmsr only the EE bit is set and we get an interrupt, we 
end up in transfer_to_handler(), check the flag, it is set, so we branch 
to power_save_6xx_restore(). There we clear NAP/DOZE and just jump to 
transfer_to_handler_cont(). Why did you say we'd miss the check for 
need_resched (on IRC)? How is this case difference from if we really did 
go to NAP / DOZE?

Are there other places in the kernel where we rely on setting MSR:POW and 
some other bit atomically?
Indeed, the napping "recovery" code might save us here... funny, as it
wasn't implemented to handle that case at all...

Ben.
Keyboard shortcuts
hback out one level
jnext message in thread
kprevious message in thread
ldrill in
Escclose help / fold thread tree
?toggle this help