Re: Chenging 2 bits in MSR in ppc6xx_idle() with 1 command?
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Date: 2006-12-26 23:48:55
On Mon, 2006-12-25 at 21:07 +0100, Guennadi Liakhovetski wrote:
Hi Here's a code fragment from ppc6xx_idle(), which should send the CPU into a powersaving mode (DOZE or NAP) and re-enable interrupts after a local_irq_disable(): mfmsr r7 ori r7,r7,MSR_EE oris r7,r7,MSR_POW@h 1: sync mtmsr r7 isync b 1b Whereas MPC8245's user manual says, that when setting the MSR_POW bit in the MSR one may not set any other bit in it with the same instruction. Does this mean that the above does not actually work on those (and similar) CPUs or does it work because of the loop?
That doc bit looks a bit strange. The kernel pretty much relies on setting MSR:EE and MSR:POW atomicaly. Ben.