On Fri, 29 Jun 2001, Dan Malek wrote:

jtm@smoothsmoothie.com wrote:

quoted

.... The buffer memory will get filled
via DMA, and therefore must not be cached.

Huh????  The 8260 is cache coherent, you don't need to do that.

For processors that are not cache coherent (4xx and 8xx), there
are standard 'consistent_alloc()' functions available.

Dan, Wwhere are the consistent_alloc functions? I just did a grep of the
entire source tree (it's about 2 weeks old 2_4_devel) and was unable to
find any consistent_* functions except for in the sparc and arm
architectures. There were pci_consistent_ functions under ppc, but I
assume that that requires a pci bus, which I do not have.

Thanks,
--Gus


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