I've been looking at the code for the i82596 ethernet controller a bit
more and think that (thank god) it provides a better base for my board's
driver than I initially though.
But...
Our board is 603e based, with non functional hardware snooping. This is
not too much a problem for this chip- it supports writing to a block of
shared memory marked as non-cachable in lieu of using snooping. In fact,
our vxworks port for the board uses a whopping half meg memory region for
this purpose (seems a bit large to me, but I wasn't involved with that
port). What's more, the driver in the kernel seems to work using a shared
memory region as well. This is architecturally good. Unfortunately, I am
unable to figure out how to mark an area of memory as non-cachable.
The existing driver was written for 68k hardware, and therefore uses calls
that are non-existant in the ppc port:
#ifdef __mc68000__
cache_push(virt_to_phys((void *)(dev->mem_start)), 4096);
cache_clear(virt_to_phys((void *)(dev->mem_start)), 4096);
kernel_set_cachemode((void *)(dev->mem_start), 4096, IOMAP_NOCACHE_SER);
#endif
Therefore, my concise question is most likely: what are the equivalent
functions for a 603e based board? (I assume that the two cache_ functions
are comprable to flush_instruction_cache, but am probably wrong about
that, so I blatantly make the error hear so that someone will correct my
ignorance :)
Thanks,
--Gus
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I am looking for a solution to a similar problem. I am writing a
driver for an FCC on the 8260 in transparent mode, and need
to allocate buffer memory. The buffer memory will get filled
via DMA, and therefore must not be cached. Will the following work
correctly?
vaddr = kmalloc(BUF_SIZE, GFP_DMA);
paddr = __pa(vaddr);
Thanks.
--
Jay Monkman The truth knocks on the door and you say "Go away, I'm
monkman@jump.net looking for the truth," and so it goes away. Puzzling.
- from _Zen_and_the_Art_of_Motorcycle_Maintenance_
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
Did yo ever get a reply to this? That sounds like just what I want to do
(well, it sounds just like what our vxworks code does to do what I want to
do, which I guess is good enough).
TIA,
--Gus
On Tue, 26 Jun 2001 jtm@smoothsmoothie.com wrote:
I am looking for a solution to a similar problem. I am writing a
driver for an FCC on the 8260 in transparent mode, and need
to allocate buffer memory. The buffer memory will get filled
via DMA, and therefore must not be cached. Will the following work
correctly?
vaddr = kmalloc(BUF_SIZE, GFP_DMA);
paddr = __pa(vaddr);
Thanks.
--
Jay Monkman The truth knocks on the door and you say "Go away, I'm
monkman@jump.net looking for the truth," and so it goes away. Puzzling.
- from _Zen_and_the_Art_of_Motorcycle_Maintenance_
.... The buffer memory will get filled
via DMA, and therefore must not be cached.
Huh???? The 8260 is cache coherent, you don't need to do that.
For processors that are not cache coherent (4xx and 8xx), there
are standard 'consistent_alloc()' functions available.
Are those functions in the code for the 6xx proceesors? I have a 603e with
a broken memory controller- it does everything (or so I am assured) except
support atomic functions (ie, no memory coherency). If they are not in the
codo, are they at least portable to the 6xx?
Thanks,
--Gus
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
.... The buffer memory will get filled
via DMA, and therefore must not be cached.
Huh???? The 8260 is cache coherent, you don't need to do that.
For processors that are not cache coherent (4xx and 8xx), there
are standard 'consistent_alloc()' functions available.
Dan, Wwhere are the consistent_alloc functions? I just did a grep of the
entire source tree (it's about 2 weeks old 2_4_devel) and was unable to
find any consistent_* functions except for in the sparc and arm
architectures. There were pci_consistent_ functions under ppc, but I
assume that that requires a pci bus, which I do not have.
Thanks,
--Gus
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
From: Dan Malek <hidden> Date: 2001-06-29 07:39:57
jtm@smoothsmoothie.com wrote:
.... The buffer memory will get filled
via DMA, and therefore must not be cached.
Huh???? The 8260 is cache coherent, you don't need to do that.
For processors that are not cache coherent (4xx and 8xx), there
are standard 'consistent_alloc()' functions available.
-- Dan
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
On Fri, Jun 29, 2001 at 03:39:57AM -0400, Dan Malek wrote:
jtm@smoothsmoothie.com wrote:
quoted
.... The buffer memory will get filled
via DMA, and therefore must not be cached.
Huh???? The 8260 is cache coherent, you don't need to do that.
OK. I've had more experience with the 860, and just assumed the
8260 had the same no cache requirement on DMA. Thanks.
--
Jay Monkman The truth knocks on the door and you say "Go away, I'm
monkman@jump.net looking for the truth," and so it goes away. Puzzling.
- from _Zen_and_the_Art_of_Motorcycle_Maintenance_
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
From: Paul White <hidden> Date: 2001-06-29 17:45:18
Dan,
It doesn't just matter if the CPU is cache coherent or not. If you have a
System Controller, which controls
the memory, and the DMA'ing device is off of that System Controller, then
the controller must support
Snooping, to generate CleanBlock,FlushBlock, or KillBlock transactions on
the CPU's bus.
The CPU supporting cache coherency just means it supports at least one of
these snoop transactions.
Someone still needs to generate these transactions.
Paul W.
At 03:39 AM 6/29/2001 -0400, Dan Malek wrote:
jtm@smoothsmoothie.com wrote:
quoted
.... The buffer memory will get filled
via DMA, and therefore must not be cached.
Huh???? The 8260 is cache coherent, you don't need to do that.
For processors that are not cache coherent (4xx and 8xx), there
are standard 'consistent_alloc()' functions available.
-- Dan
-------------------------------------------------------------
Network Robots, Inc. /--\ Paul H. White
/ ____ \
4695 Chabot Dr. #200 / ( oo ) \ Software Developer
Pleasanton, CA 94588 / ---- \ Engineering
(925) 924-8600 \ ---- / (925) 580-4883
\ V--V /
\ /
\--/
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
From: Paul White <hidden> Date: 2001-06-29 17:48:45
Btw...Where are these "consistent_alloc()" functions? I've not seen theses
anywhere.
I also can't imagine how they would possibly work on any CPU using BATs.
Since the BAT is setup as cacheable space, you can't just take a "chunk"
of it and make it non-cacheable. Not possible.
Now, yes, for the 4xx and 8xx proccessors that don't use BATs, I would
assume that when you do one of these "non-cache" allocs, it would
simply allocate you a batch of 4k pages, and set them as Caching
Inhibited.
Is there something I'm missing here?
Paul W.
At 03:39 AM 6/29/2001 -0400, Dan Malek wrote:
jtm@smoothsmoothie.com wrote:
quoted
.... The buffer memory will get filled
via DMA, and therefore must not be cached.
Huh???? The 8260 is cache coherent, you don't need to do that.
For processors that are not cache coherent (4xx and 8xx), there
are standard 'consistent_alloc()' functions available.
-- Dan
-------------------------------------------------------------
Network Robots, Inc. /--\ Paul H. White
/ ____ \
4695 Chabot Dr. #200 / ( oo ) \ Software Developer
Pleasanton, CA 94588 / ---- \ Engineering
(925) 924-8600 \ ---- / (925) 580-4883
\ V--V /
\ /
\--/
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
From: Paul White <hidden> Date: 2001-06-29 17:55:29
Jay,
Basically, on any CPU, DMA requires either no cache, or at least a cache
coherent
system. Cache Coherency is a two-part thing, the CPU must support it, the
memory (system) controller. If the memory controller doesn't generate the
proper
cache coherency snoop cycles, the CPU still has no idea to flush or invalidate
cache lines.
Paul W.
At 11:30 AM 6/29/2001 -0500, jtm@smoothsmoothie.com wrote:
On Fri, Jun 29, 2001 at 03:39:57AM -0400, Dan Malek wrote:
quoted
jtm@smoothsmoothie.com wrote:
quoted
.... The buffer memory will get filled
via DMA, and therefore must not be cached.
Huh???? The 8260 is cache coherent, you don't need to do that.
OK. I've had more experience with the 860, and just assumed the
8260 had the same no cache requirement on DMA. Thanks.
--
Jay Monkman The truth knocks on the door and you say "Go away, I'm
monkman@jump.net looking for the truth," and so it goes away. Puzzling.
- from _Zen_and_the_Art_of_Motorcycle_Maintenance_
-------------------------------------------------------------
Network Robots, Inc. /--\ Paul H. White
/ ____ \
4695 Chabot Dr. #200 / ( oo ) \ Software Developer
Pleasanton, CA 94588 / ---- \ Engineering
(925) 924-8600 \ ---- / (925) 580-4883
\ V--V /
\ /
\--/
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
From: Dan Malek <hidden> Date: 2001-07-01 05:04:06
"Justin (Gus) Hurwitz" wrote:
Dan, Wwhere are the consistent_alloc functions?
They are supposed to be in arch/ppc/mm/ioremap.c, but there has been
lots of work done there recently. I haven't worked in the tree
recently,
so I'll take a look.
-- Dan
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
From: Dan Malek <hidden> Date: 2001-07-01 05:09:04
Paul White wrote:
Is there something I'm missing here?
Yeah...you can run 'nobats' as a start option and get the memory
mapped as pages (or fix your system so cache coherency works :-).
-- Dan
** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/
From: Paul White <hidden> Date: 2001-07-01 06:45:08
Dan,
hehe.. I went the harder way, and worked around the dcbz instructions
to allow me to disable data cache all together.
Btw, we also fixed our Cache Coherency problem on Friday. It happened
to be a bug in our system controller chip. They found it and gave us
a work-around.
Thanks,
Paul W.
On Sun, 1 Jul 2001, Dan Malek wrote:
Paul White wrote:
quoted
Is there something I'm missing here?
Yeah...you can run 'nobats' as a start option and get the memory
mapped as pages (or fix your system so cache coherency works :-).
-- Dan