On 2021-08-17 22:56, Prasad Malisetty wrote:

On 2021-08-10 09:38, Prasad Malisetty wrote:

quoted

On the SC7280, By default the clock source for pcie_1_pipe is
TCXO for gdsc enable. But after the PHY is initialized, the clock
source must be switched to gcc_pcie_1_pipe_clk from TCXO.

Signed-off-by: Prasad Malisetty <redacted>
---
 drivers/pci/controller/dwc/pcie-qcom.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c

b/drivers/pci/controller/dwc/pcie-qcom.c
index 8a7a300..39e3b21 100644

--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c

@@ -166,6 +166,8 @@ struct qcom_pcie_resources_2_7_0 {
 	struct regulator_bulk_data supplies[2];
 	struct reset_control *pci_reset;
 	struct clk *pipe_clk;
+	struct clk *gcc_pcie_1_pipe_clk_src;
+	struct clk *phy_pipe_clk;
 };

 union qcom_pcie_resources {

@@ -1167,6 +1169,16 @@ static int qcom_pcie_get_resources_2_7_0(struct

qcom_pcie *pcie)
 	if (ret < 0)
 		return ret;

+	if (of_device_is_compatible(dev->of_node, "qcom,pcie-sc7280")) {
+		res->gcc_pcie_1_pipe_clk_src = devm_clk_get(dev, "pipe_mux");
+		if (IS_ERR(res->gcc_pcie_1_pipe_clk_src))
+			return PTR_ERR(res->gcc_pcie_1_pipe_clk_src);
+
+		res->phy_pipe_clk = devm_clk_get(dev, "phy_pipe");
+		if (IS_ERR(res->phy_pipe_clk))
+			return PTR_ERR(res->phy_pipe_clk);
+	}
+

Hi All,

Greetings!

I would like to check is there any other better approach instead of
compatible method here as well or is it fine to use compatible method.

Thanks
-Prasad

quoted

 	res->pipe_clk = devm_clk_get(dev, "pipe");
 	return PTR_ERR_OR_ZERO(res->pipe_clk);
 }

@@ -1255,6 +1267,12 @@ static void qcom_pcie_deinit_2_7_0(struct

qcom_pcie *pcie)
 static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
 {
 	struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
+	struct dw_pcie *pci = pcie->pci;
+	struct device *dev = pci->dev;
+	struct device_node *node = dev->of_node;
+
+	if (of_property_read_bool(node, "pipe-clk-source-switch"))
+		clk_set_parent(res->gcc_pcie_1_pipe_clk_src, res->phy_pipe_clk);

 	return clk_prepare_enable(res->pipe_clk);
 }

Hi,

Kindly provide your inputs and confirmation on latest queries, I will 
share new patch version.

Thanks
-Prasad