Thread (25 messages) 25 messages, 5 authors, 2021-09-09

Re: [PATCH v5 2/4] arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes

From: Stephen Boyd <hidden>
Date: 2021-08-10 19:25:41
Also in: linux-arm-msm, linux-devicetree, lkml

Quoting Prasad Malisetty (2021-08-09 21:08:34)
quoted hunk ↗ jump to hunk
Add PCIe controller and PHY nodes for sc7280 SOC.

Signed-off-by: Prasad Malisetty <redacted>
---
 arch/arm64/boot/dts/qcom/sc7280.dtsi | 126 +++++++++++++++++++++++++++++++++++
 1 file changed, 126 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 53a21d0..4500d88 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -16,6 +16,7 @@
 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
 #include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/gpio/gpio.h>
Please sort this alphabetically, gpio comes before reset at the least.
quoted hunk ↗ jump to hunk
 / {
        interrupt-parent = <&intc>;
@@ -586,6 +587,119 @@
                        qcom,bcm-voters = <&apps_bcm_voter>;
                };

+               pcie1: pci@1c08000 {
+                       compatible = "qcom,pcie-sc7280", "qcom,pcie-sm8250", "snps,dw-pcie";
+                       reg = <0 0x01c08000 0 0x3000>,
+                             <0 0x40000000 0 0xf1d>,
+                             <0 0x40000f20 0 0xa8>,
+                             <0 0x40001000 0 0x1000>,
+                             <0 0x40100000 0 0x100000>;
+
+                       reg-names = "parf", "dbi", "elbi", "atu", "config";
+                       device_type = "pci";
+                       linux,pci-domain = <1>;
+                       bus-range = <0x00 0xff>;
+                       num-lanes = <2>;
+                       pipe-clk-source-switch;
I'd rather not have this DT property, but key it off the compatible
string.
+
+                       #address-cells = <3>;
+                       #size-cells = <2>;
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