[PATCH v2 3/6] staging: mt7621-pci: use {readl|writel}_relaxed instead of readl/writel
From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Date: 2021-06-06 16:14:05
Subsystem:
staging subsystem, the rest · Maintainers:
Greg Kroah-Hartman, Linus Torvalds
The driver does not perform DMA, so it's safe to use the relaxed version for both readl and writel operations. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> --- drivers/staging/mt7621-pci/pci-mt7621.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index b83c338a2e3d..8d14d0f9f769 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c@@ -109,32 +109,32 @@ struct mt7621_pcie { static inline u32 pcie_read(struct mt7621_pcie *pcie, u32 reg) { - return readl(pcie->base + reg); + return readl_relaxed(pcie->base + reg); } static inline void pcie_write(struct mt7621_pcie *pcie, u32 val, u32 reg) { - writel(val, pcie->base + reg); + writel_relaxed(val, pcie->base + reg); } static inline void pcie_rmw(struct mt7621_pcie *pcie, u32 reg, u32 clr, u32 set) { - u32 val = readl(pcie->base + reg); + u32 val = readl_relaxed(pcie->base + reg); val &= ~clr; val |= set; - writel(val, pcie->base + reg); + writel_relaxed(val, pcie->base + reg); } static inline u32 pcie_port_read(struct mt7621_pcie_port *port, u32 reg) { - return readl(port->base + reg); + return readl_relaxed(port->base + reg); } static inline void pcie_port_write(struct mt7621_pcie_port *port, u32 val, u32 reg) { - writel(val, port->base + reg); + writel_relaxed(val, port->base + reg); } static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
@@ -151,7 +151,7 @@ static void __iomem *mt7621_pcie_map_bus(struct pci_bus *bus, u32 address = mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where); - writel(address, pcie->base + RALINK_PCI_CONFIG_ADDR); + writel_relaxed(address, pcie->base + RALINK_PCI_CONFIG_ADDR); return pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3); }
--
2.25.1