[PATCH v2 2/6] staging: mt7621-pci: remove 'RALINK_PCI_BAR0SETUP_ADDR' definition
From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Date: 2021-06-06 16:14:04
Subsystem:
staging subsystem, the rest · Maintainers:
Greg Kroah-Hartman, Linus Torvalds
Instead of define RALINK_PCI_BAR0SETUP_ADDR just use standard pci defnition for this which is 'PCI_BASE_ADDRESS_0'. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> --- drivers/staging/mt7621-pci/pci-mt7621.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index c14fc48e74fc..b83c338a2e3d 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c@@ -47,7 +47,6 @@ #define MT7621_PCIE_OFFSET 0x2000 #define MT7621_NEXT_PORT 0x1000 -#define RALINK_PCI_BAR0SETUP_ADDR 0x0010 #define RALINK_PCI_ID 0x0030 #define RALINK_PCI_CLASS 0x0034 #define RALINK_PCI_SUBID 0x0038
@@ -494,7 +493,7 @@ static void mt7621_pcie_enable_port(struct mt7621_pcie_port *port) /* map 2G DDR region */ pcie_write(pcie, PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE, - offset + RALINK_PCI_BAR0SETUP_ADDR); + offset + PCI_BASE_ADDRESS_0); /* configure class code and revision ID */ pcie_write(pcie, PCIE_CLASS_CODE | PCIE_REVISION_ID,
--
2.25.1