Hi Krzysztof,

-----Original Message-----
From: Krzysztof Kozlowski <krzk@kernel.org>
Sent: 06 July 2025 03:14 PM
To: Pritam Manohar Sutar <redacted>
Cc: vkoul@kernel.org; kishon@kernel.org; robh@kernel.org;
krzk+dt@kernel.org; conor+dt@kernel.org; alim.akhtar@samsung.com;
andre.draszik@linaro.org; peter.griffin@linaro.org; neil.armstrong@linaro.org;
kauschluss@disroot.org; ivo.ivanov.ivanov1@gmail.com;
m.szyprowski@samsung.com; s.nawrocki@samsung.com; linux-
phy@lists.infradead.org; devicetree@vger.kernel.org; linux-
kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-samsung-
soc@vger.kernel.org; rosa.pila@samsung.com; dev.tailor@samsung.com;
faraz.ata@samsung.com; muhammed.ali@samsung.com;
selvarasu.g@samsung.com
Subject: Re: [PATCH v4 5/6] dt-bindings: phy: samsung,usb3-drd-phy: add
ExynosAutov920 combo SS phy

On Tue, Jul 01, 2025 at 05:37:05PM +0530, Pritam Manohar Sutar wrote:

quoted

This phy supports USB3.1 SSP+(10Gbps) protocol and is backwards

Agian, this?

quoted

compatible to the USB3.0 SS(5Gbps). 'Add-on USB2.0' phy is required to
support USB2.0 HS(480Mbps), FS(12Mbps) and LS(1.5Mbps) data rates.
These two phys are combined to form a combo phy.

Add a dedicated compatible string for USB combo SS phy found in this
SoC. The SoC requires two clocks, named "phy" and "ref" and various
power supplies (regulators) for the internal circuitry to work.
The required voltages are:
* avdd075_usb - 0.75v
* avdd18_usb20 - 1.8v
* avdd33_usb20 - 3.3v

One more commitm message completely copy-pasted and completely
uninforming. The voltages are irrelevant. Explain the architecture. This should be
just one patch with proper full description.

quoted

Add schema only for 'USB3.1 SSP+' SS phy in this commit.

Why only? Add everything, describe everything, but not what voltages you have
there but the architecture of the PHY.

Will combine patch 3 (combo HS phy) & 5(combo SS phy) to describe combo phy and even will add some details as mentioned in cover letter.

Best regards,
Krzysztof

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