On Thu, 2011-08-25 at 13:46 -0500, Christoph Lameter wrote:

RISC cpus have instruction to construct complex atomic actions by the cpu
as I have shown before for ARM. 

Right, but it only makes sense if the whole thing remains cheaper than
the trivial implementation already available.

For instance, the ARM LL/SC constraints pretty much mandate we do
preempt_disable()/preempt_enable() around them, at which point the point
of doing LL/SC is gone (except maybe for the irqsafe_this_cpu_* stuff).

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