On Thu, Dec 16, 2021 at 3:27 PM Jiaxun Yang [off-list ref] wrote:

在 2021/12/16 14:18, Arnd Bergmann 写道:

quoted

quoted

It got refactored by this patch as TLB entries are expensive on MIPS,
also the size of IO range doesn't always fits a page.

Are PIO accesses common enough that the TLB entry makes a difference?
I would imagine that on most systems with a PCI bus, there is not even
a single device that exposes an I/O resource, and even on those devices that
do, the kernel drivers tend to pick MMIO whenever both are available.

Actually that was claimed by the author of this patch :-)
I can understand the point. As he is working on a ramips system utlizes
1004Kec,
which has only 32 TLB entries, saving a entry can give considerable
improvement.

Ok

For Loongson as we have legacy i8042/i8259 which can only be accessed via
PIO, the access is very common.

Ah, right. It makes a lot of sense that anything based on ISA PC peripherals
would need it, regardless of the PCI support.

       Arnd