[PATCH v2 3/9] dt-bindings: arm: mediatek: add definition for mt8195 mmsys
STALE1903d
From: jason-jh.lin <hidden>
Date: 2021-07-10 11:43:05
Also in:
linux-arm-kernel
Subsystem:
open firmware and flattened device tree bindings, the rest · Maintainers:
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds
There are 2 display hardware path in mt8195, namely vdosys0 and vdosys1, so add their definition in mtk-mmsys documentation. Signed-off-by: jason-jh.lin <redacted> --- .../bindings/arm/mediatek/mediatek,mmsys.txt | 15 +++++++++++++++ 1 file changed, 15 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
index 9712a6831fab..be1761010d3c 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt@@ -17,6 +17,8 @@ Required Properties: - "mediatek,mt8173-mmsys", "syscon" - "mediatek,mt8183-mmsys", "syscon" - "mediatek,mt8192-mmsys", "syscon" + - "mediatek,mt8195-vdosys0", "syscon" + - "mediatek,mt8195-vdosys1", "syscon" - #clock-cells: Must be 1 For the clock control, the mmsys controller uses the common clk binding from
@@ -30,3 +32,16 @@ mmsys: syscon@14000000 { reg = <0 0x14000000 0 0x1000>; #clock-cells = <1>; }; + +vdosys0: syscon@1c01a000 { + compatible = "mediatek,mt8195-vdosys0", "syscon"; + reg = <0 0x1c01a000 0 0x1000>; + #clock-cells = <1>; +}; + +vdosys1: syscon@1c100000 { + compatible = "mediatek,mt8195-vdosys1", "syscon"; + reg = <0 0x1c100000 0 0x1000>; + #clock-cells = <1>; +}; +
--
2.18.0
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