Hi Ian,

On Wed, Jun 9, 2021 at 2:28 PM Ian Arkver [off-list ref] wrote:

quoted

Page 55 of the ADV7280-M HW Ref Manual shows how the CLK and DATA lanes
can be (separately) forced into Ultra Low Power State. It mentions that
when exiting ULPS it transmits the ULPS exit sequence, though it doesn't
define what that sequence is. Perhaps this sequence includes
transitioning through LP-11 enough to keep the CSI-2 RX happy?

I measured the CLK and DATA lines and they are stuck at 0.

LP-11 means CLK and DATA at 1, right?

So this is what I tried as per your suggestion:

--- a/drivers/media/i2c/adv7180.c
+++ b/drivers/media/i2c/adv7180.c

@@ -505,6 +505,8 @@ static int adv7180_s_power(struct v4l2_subdev *sd, int on)
         struct adv7180_state *state = to_state(sd);
         int ret;

         ret = mutex_lock_interruptible(&state->mutex);
         if (ret)
                 return ret;

@@ -512,6 +514,20 @@ static int adv7180_s_power(struct v4l2_subdev *sd, int on)
         ret = adv7180_set_power(state, on);
         if (ret == 0)
                 state->powered = on;
+
+       if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
+               pr_err("**** Put MIPI CSI in LP-11\n");
+               adv7180_csi_write(state, 0x26, 0x00);
+               msleep(100);
+               adv7180_csi_write(state, 0x26, 0x80);
+               msleep(100);
+               adv7180_csi_write(state, 0x26, 0xc0);
+               msleep(100);
+               adv7180_csi_write(state, 0x26, 0xe0);
+               msleep(100);
+               adv7180_csi_write(state, 0x26, 0xf0);
+               msleep(100);
+       }