-----Original Message-----
From: John Madieu <john.madieu.xa@bp.renesas.com>
Sent: 27 February 2026 15:33
Subject: [PATCH v7 12/15] PCI: rzg3s-host: Add support for RZ/G3E PCIe controller

Add support for the PCIe controller found in RZ/G3E SoCs to the existing RZ/G3S PCIe host driver. The
RZ/G3E PCIe controller is similar to the RZ/G3S's, with the following key differences:

 - Supports PCIe Gen3 (8.0 GT/s) link speeds alongside Gen2 (5.0 GT/s)
 - Uses a different reset control mechanism via AXI registers instead
   of the Linux reset framework
 - Requires specific SYSC configuration for link state control and
   Root Complex mode selection

Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---

Changes:

v7:
 - Renamed RZG3E_PCI_RESET* defines to RZG3S_PCI_RESET* as these
   registers are shared with upcoming SoCs (RZ/V2H, RZ/T2N, RZ/N2H),
   dropped associated "RZ/G3E specific registers" comment
 - Dropped "RZ/G3E SoC-specific config implementations" comment
 - Unified function naming to rzg3e_pcie_config_{pre_init,post_init,
   deinit}() and rzg3s_pcie_config_{post_init,deinit}()
 - Simplified comments as per Claudiu's suggestions
 - Used local mask variables for compactness within 80-char limit
 - Fixed L1_ALLOW error path: goto config_deinit_and_refclk since
   port refclk is already enabled
 - Fixed resume: reordered MODE before RST_RSM_B to match probe
   sequence, fixing error path handling

v6:
  - Use rzg3s_sysc_config_func() with per-function calls instead of
    rzg3s_sysc_config() with -1 skip pattern, as suggested by Claudiu
  - Extend enum rzg3s_sysc_func_id with L1_ALLOW and MODE entries
  - Use regmap_update_bits() consistently for all SYSC accesses
  - Shorten comment to "Put controller in RC mode and de-assert RST_RSM_B."
  - Drop "Enable ASPM L1 transition" comment (function ID is self-documenting)

v5:
  - Introduce rzg3s_sysc_config() helper for sys configuration

v4: No changes
v3: No changes

 drivers/pci/controller/pcie-rzg3s-host.c | 90 ++++++++++++++++++++++++
 1 file changed, 90 insertions(+)

diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c
index 44ce056d62c6..b7f92f5aee4a 100644
--- a/drivers/pci/controller/pcie-rzg3s-host.c
+++ b/drivers/pci/controller/pcie-rzg3s-host.c

@@ -111,6 +111,15 @@
 #define RZG3S_PCI_PERM_CFG_HWINIT_EN		BIT(2)
 #define RZG3S_PCI_PERM_PIPE_PHY_REG_EN		BIT(1)

+#define RZG3S_PCI_RESET				0x310