[PATCH v7 04/15] clk: renesas: r9a09g047: Add PCIe clocks and reset
From: John Madieu <john.madieu.xa@bp.renesas.com>
Date: 2026-02-27 15:33:31
Also in:
linux-clk, linux-pci, linux-renesas-soc
Subsystem:
common clk framework, renesas clock drivers, the rest · Maintainers:
Michael Turquette, Stephen Boyd, Geert Uytterhoeven, Linus Torvalds
Add necessary clocks and reset entries for the PCIe controller Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> --- Changes: v7: - Reused standard clock/reset definition macros v6: No changes v5: No changes v4: No changes v3: - Collected Rb tag - Preserved sort order (by _onindex, _onbit); v2: - Fixed clock names - Used assert-variant for reset drivers/clk/renesas/r9a09g047-cpg.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c
index 1e9896742a06..6f5c4b0a6256 100644
--- a/drivers/clk/renesas/r9a09g047-cpg.c
+++ b/drivers/clk/renesas/r9a09g047-cpg.c@@ -424,6 +424,10 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = { BUS_MSTOP(8, BIT(6))), DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3, BUS_MSTOP(8, BIT(6))), + DEF_MOD("pcie_0_aclk", CLK_PLLDTY_ACPU_DIV2, 12, 4, 6, 4, + BUS_MSTOP(1, BIT(15))), + DEF_MOD("pcie_0_clk_pmu", CLK_PLLDTY_ACPU_DIV2, 12, 5, 6, 5, + BUS_MSTOP(1, BIT(15))), DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18, BUS_MSTOP(9, BIT(4))), DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
@@ -503,6 +507,7 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = { DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */ DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */ DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */ + DEF_RST(11, 2, 5, 3), /* PCIE_0_ARESETN */ DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */ DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */ DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
--
2.25.1