[PATCH v7 08/15] PCI: rzg3s-host: Make configuration reset lines optional
From: John Madieu <john.madieu.xa@bp.renesas.com>
Date: 2026-02-27 15:33:55
Also in:
linux-clk, linux-pci, linux-renesas-soc
Subsystem:
pci native host bridge and endpoint drivers, pci subsystem, pcie driver for renesas rz/g3s series, the rest · Maintainers:
Lorenzo Pieralisi, Krzysztof Wilczyński, Manivannan Sadhasivam, Bjorn Helgaas, Claudiu Beznea, Linus Torvalds
Some SoC variants such as RZ/G3E handle configuration reset control through PCIe AXI registers instead of dedicated reset lines. Make cfg_resets optional by using devm_reset_control_bulk_get_optional_exclusive() to allow SoCs to use alternative or complementary reset control mechanisms. Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> --- changes: v7: Fixed checkpatch commit message line length warnings v6: No changes v5: No changes v4: No changes v3: No changes v2: Collected Rb tag. drivers/pci/controller/pcie-rzg3s-host.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c
index b8a3abf7b6cc..c741d5ac2594 100644
--- a/drivers/pci/controller/pcie-rzg3s-host.c
+++ b/drivers/pci/controller/pcie-rzg3s-host.c@@ -1188,9 +1188,9 @@ static int rzg3s_pcie_resets_prepare_and_get(struct rzg3s_pcie_host *host) if (ret) return ret; - return devm_reset_control_bulk_get_exclusive(host->dev, - data->num_cfg_resets, - host->cfg_resets); + return devm_reset_control_bulk_get_optional_exclusive(host->dev, + data->num_cfg_resets, + host->cfg_resets); } static int rzg3s_pcie_host_parse_port(struct rzg3s_pcie_host *host)
--
2.25.1