[PATCH v3 6/6] arm64: dts: st: Add boot phase tags for STMicroelectronics mp2 boards
From: Patrice Chotard <patrice.chotard@foss.st.com>
Date: 2026-01-08 17:16:13
Also in:
linux-arm-kernel, lkml
Subsystem:
arm/stm32 architecture, the rest · Maintainers:
Maxime Coquelin, Alexandre Torgue, Linus Torvalds
The bootph-all flag was introduced in dt-schema (dtschema/schemas/bootph.yaml) to define node usage across different boot phases. To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be present in all boot stages, so add missing bootph-all phase flag to these nodes to support SD boot. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> --- arch/arm64/boot/dts/st/stm32mp211.dtsi | 7 +++++++ arch/arm64/boot/dts/st/stm32mp215f-dk.dts | 1 + arch/arm64/boot/dts/st/stm32mp231.dtsi | 22 ++++++++++++++++++++++ arch/arm64/boot/dts/st/stm32mp235f-dk.dts | 11 +++++++++++ arch/arm64/boot/dts/st/stm32mp251.dtsi | 25 +++++++++++++++++++++++++ arch/arm64/boot/dts/st/stm32mp255.dtsi | 3 ++- arch/arm64/boot/dts/st/stm32mp257f-dk.dts | 11 +++++++++++ arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 11 +++++++++++ 8 files changed, 90 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/st/stm32mp211.dtsi b/arch/arm64/boot/dts/st/stm32mp211.dtsi
index bf888d60cd4f..81b6a71fc032 100644
--- a/arch/arm64/boot/dts/st/stm32mp211.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp211.dtsi@@ -50,6 +50,7 @@ firmware { optee { compatible = "linaro,optee-tz"; method = "smc"; + bootph-all; }; scmi: scmi {
@@ -57,15 +58,18 @@ scmi: scmi { #address-cells = <1>; #size-cells = <0>; linaro,optee-channel-id = <0>; + bootph-all; scmi_clk: protocol@14 { reg = <0x14>; #clock-cells = <1>; + bootph-all; }; scmi_reset: protocol@16 { reg = <0x16>; #reset-cells = <1>; + bootph-all; }; }; };
@@ -73,6 +77,7 @@ scmi_reset: protocol@16 { psci { compatible = "arm,psci-1.0"; method = "smc"; + bootph-all; }; timer {
@@ -92,6 +97,7 @@ soc@0 { interrupt-parent = <&intc>; #address-cells = <1>; #size-cells = <2>; + bootph-all; rifsc: bus@42080000 { compatible = "simple-bus";
@@ -100,6 +106,7 @@ rifsc: bus@42080000 { dma-ranges; #address-cells = <1>; #size-cells = <2>; + bootph-all; usart2: serial@400e0000 { compatible = "st,stm32h7-uart";
diff --git a/arch/arm64/boot/dts/st/stm32mp215f-dk.dts b/arch/arm64/boot/dts/st/stm32mp215f-dk.dts
index 7bdaeaa5ab0f..bc366639744a 100644
--- a/arch/arm64/boot/dts/st/stm32mp215f-dk.dts
+++ b/arch/arm64/boot/dts/st/stm32mp215f-dk.dts@@ -45,5 +45,6 @@ &arm_wdt { }; &usart2 { + bootph-all; status = "okay"; };
diff --git a/arch/arm64/boot/dts/st/stm32mp231.dtsi b/arch/arm64/boot/dts/st/stm32mp231.dtsi
index 88e214d395ab..075b4419d3ae 100644
--- a/arch/arm64/boot/dts/st/stm32mp231.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp231.dtsi@@ -57,6 +57,7 @@ optee: optee { method = "smc"; interrupt-parent = <&intc>; interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + bootph-all; }; scmi {
@@ -64,15 +65,18 @@ scmi { #address-cells = <1>; #size-cells = <0>; linaro,optee-channel-id = <0>; + bootph-all; scmi_clk: protocol@14 { reg = <0x14>; #clock-cells = <1>; + bootph-all; }; scmi_reset: protocol@16 { reg = <0x16>; #reset-cells = <1>; + bootph-all; }; scmi_voltd: protocol@17 {
@@ -114,6 +118,7 @@ scmi_vdda18adc: regulator@7 { psci { compatible = "arm,psci-1.0"; method = "smc"; + bootph-all; cpu0_pd: power-domain-cpu0 { #power-domain-cells = <0>;
@@ -146,6 +151,7 @@ soc@0 { interrupt-parent = <&intc>; #address-cells = <1>; #size-cells = <1>; + bootph-all; hpdma: dma-controller@40400000 { compatible = "st,stm32mp25-dma3";
@@ -223,6 +229,7 @@ rifsc: bus@42080000 { #address-cells = <1>; #size-cells = <1>; #access-controller-cells = <1>; + bootph-all; i2s2: audio-controller@400b0000 { compatible = "st,stm32mp25-i2s";
@@ -760,6 +767,7 @@ bsec: efuse@44000000 { reg = <0x44000000 0x1000>; #address-cells = <1>; #size-cells = <1>; + bootph-all; part_number_otp@24 { reg = <0x24 0x4>;
@@ -857,6 +865,7 @@ rcc: clock-controller@44200000 { <&scmi_clk CK_SCMI_PLL3>, <&clk_dsi_txbyte>; access-controllers = <&rifsc 156>; + bootph-all; }; exti1: interrupt-controller@44220000 {
@@ -955,6 +964,7 @@ exti1: interrupt-controller@44220000 { syscfg: syscon@44230000 { compatible = "st,stm32mp23-syscfg", "syscon"; reg = <0x44230000 0x10000>; + bootph-all; }; pinctrl: pinctrl@44240000 {
@@ -965,6 +975,7 @@ pinctrl: pinctrl@44240000 { interrupt-parent = <&exti1>; st,syscfg = <&exti1 0x60 0xff>; pins-are-numbered; + bootph-all; gpioa: gpio@44240000 { reg = <0x0 0x400>;
@@ -974,6 +985,7 @@ gpioa: gpio@44240000 { #interrupt-cells = <2>; clocks = <&scmi_clk CK_SCMI_GPIOA>; st,bank-name = "GPIOA"; + bootph-all; status = "disabled"; };
@@ -985,6 +997,7 @@ gpiob: gpio@44250000 { #interrupt-cells = <2>; clocks = <&scmi_clk CK_SCMI_GPIOB>; st,bank-name = "GPIOB"; + bootph-all; status = "disabled"; };
@@ -996,6 +1009,7 @@ gpioc: gpio@44260000 { #interrupt-cells = <2>; clocks = <&scmi_clk CK_SCMI_GPIOC>; st,bank-name = "GPIOC"; + bootph-all; status = "disabled"; };
@@ -1007,6 +1021,7 @@ gpiod: gpio@44270000 { #interrupt-cells = <2>; clocks = <&scmi_clk CK_SCMI_GPIOD>; st,bank-name = "GPIOD"; + bootph-all; status = "disabled"; };
@@ -1018,6 +1033,7 @@ gpioe: gpio@44280000 { #interrupt-cells = <2>; clocks = <&scmi_clk CK_SCMI_GPIOE>; st,bank-name = "GPIOE"; + bootph-all; status = "disabled"; };
@@ -1029,6 +1045,7 @@ gpiof: gpio@44290000 { #interrupt-cells = <2>; clocks = <&scmi_clk CK_SCMI_GPIOF>; st,bank-name = "GPIOF"; + bootph-all; status = "disabled"; };
@@ -1040,6 +1057,7 @@ gpiog: gpio@442a0000 { #interrupt-cells = <2>; clocks = <&scmi_clk CK_SCMI_GPIOG>; st,bank-name = "GPIOG"; + bootph-all; status = "disabled"; };
@@ -1051,6 +1069,7 @@ gpioh: gpio@442b0000 { #interrupt-cells = <2>; clocks = <&scmi_clk CK_SCMI_GPIOH>; st,bank-name = "GPIOH"; + bootph-all; status = "disabled"; };
@@ -1062,6 +1081,7 @@ gpioi: gpio@442c0000 { #interrupt-cells = <2>; clocks = <&scmi_clk CK_SCMI_GPIOI>; st,bank-name = "GPIOI"; + bootph-all; status = "disabled"; }; };
@@ -1084,6 +1104,7 @@ pinctrl_z: pinctrl@46200000 { interrupt-parent = <&exti1>; st,syscfg = <&exti1 0x60 0xff>; pins-are-numbered; + bootph-all; gpioz: gpio@46200000 { reg = <0 0x400>;
@@ -1094,6 +1115,7 @@ gpioz: gpio@46200000 { clocks = <&scmi_clk CK_SCMI_GPIOZ>; st,bank-name = "GPIOZ"; st,bank-ioport = <11>; + bootph-all; status = "disabled"; };
diff --git a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts
index c3e688068223..391494eda5e6 100644
--- a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts
+++ b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts@@ -130,7 +130,18 @@ &usart2 { pinctrl-0 = <&usart2_pins_a>; pinctrl-1 = <&usart2_idle_pins_a>; pinctrl-2 = <&usart2_sleep_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status = "okay"; }; + +&usart2_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +};
diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi
index a8e6e0f77b83..0cc3ac8bb584 100644
--- a/arch/arm64/boot/dts/st/stm32mp251.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi@@ -66,6 +66,7 @@ optee: optee { method = "smc"; interrupt-parent = <&intc>; interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + bootph-all; }; scmi {
@@ -73,15 +74,18 @@ scmi { #address-cells = <1>; #size-cells = <0>; linaro,optee-channel-id = <0>; + bootph-all; scmi_clk: protocol@14 { reg = <0x14>; #clock-cells = <1>; + bootph-all; }; scmi_reset: protocol@16 { reg = <0x16>; #reset-cells = <1>; + bootph-all; }; scmi_voltd: protocol@17 {
@@ -142,6 +146,7 @@ v2m0: v2m@48090000 { psci { compatible = "arm,psci-1.0"; method = "smc"; + bootph-all; CPU_PD0: power-domain-cpu0 { #power-domain-cells = <0>;
@@ -174,6 +179,7 @@ soc@0 { #size-cells = <1>; interrupt-parent = <&intc>; ranges = <0x0 0x0 0x0 0x80000000>; + bootph-all; hpdma: dma-controller@40400000 { compatible = "st,stm32mp25-dma3";
@@ -305,6 +311,7 @@ rifsc: bus@42080000 { #size-cells = <1>; #access-controller-cells = <1>; ranges; + bootph-all; timers2: timer@40000000 { compatible = "st,stm32mp25-timers";
@@ -1577,6 +1584,7 @@ ltdc: display-controller@48010000 { clock-names = "lcd", "bus"; resets = <&rcc LTDC_R>; access-controllers = <&rifsc 80>; + bootph-all; status = "disabled"; };
@@ -1738,6 +1746,7 @@ bsec: efuse@44000000 { reg = <0x44000000 0x1000>; #address-cells = <1>; #size-cells = <1>; + bootph-all; part_number_otp@24 { reg = <0x24 0x4>;
@@ -1842,6 +1851,7 @@ rcc: clock-controller@44200000 { <&scmi_clk CK_SCMI_PLL3>, <&clk_dsi_txbyte>; access-controllers = <&rifsc 156>; + bootph-all; }; exti1: interrupt-controller@44220000 {
@@ -1941,6 +1951,7 @@ syscfg: syscon@44230000 { compatible = "st,stm32mp25-syscfg", "syscon"; reg = <0x44230000 0x10000>; #clock-cells = <0>; + bootph-all; }; pinctrl: pinctrl@44240000 {
@@ -1951,6 +1962,7 @@ pinctrl: pinctrl@44240000 { interrupt-parent = <&exti1>; st,syscfg = <&exti1 0x60 0xff>; pins-are-numbered; + bootph-all; gpioa: gpio@44240000 { gpio-controller;
@@ -1960,6 +1972,7 @@ gpioa: gpio@44240000 { reg = <0x0 0x400>; clocks = <&scmi_clk CK_SCMI_GPIOA>; st,bank-name = "GPIOA"; + bootph-all; status = "disabled"; };
@@ -1971,6 +1984,7 @@ gpiob: gpio@44250000 { reg = <0x10000 0x400>; clocks = <&scmi_clk CK_SCMI_GPIOB>; st,bank-name = "GPIOB"; + bootph-all; status = "disabled"; };
@@ -1982,6 +1996,7 @@ gpioc: gpio@44260000 { reg = <0x20000 0x400>; clocks = <&scmi_clk CK_SCMI_GPIOC>; st,bank-name = "GPIOC"; + bootph-all; status = "disabled"; };
@@ -1993,6 +2008,7 @@ gpiod: gpio@44270000 { reg = <0x30000 0x400>; clocks = <&scmi_clk CK_SCMI_GPIOD>; st,bank-name = "GPIOD"; + bootph-all; status = "disabled"; };
@@ -2004,6 +2020,7 @@ gpioe: gpio@44280000 { reg = <0x40000 0x400>; clocks = <&scmi_clk CK_SCMI_GPIOE>; st,bank-name = "GPIOE"; + bootph-all; status = "disabled"; };
@@ -2015,6 +2032,7 @@ gpiof: gpio@44290000 { reg = <0x50000 0x400>; clocks = <&scmi_clk CK_SCMI_GPIOF>; st,bank-name = "GPIOF"; + bootph-all; status = "disabled"; };
@@ -2026,6 +2044,7 @@ gpiog: gpio@442a0000 { reg = <0x60000 0x400>; clocks = <&scmi_clk CK_SCMI_GPIOG>; st,bank-name = "GPIOG"; + bootph-all; status = "disabled"; };
@@ -2037,6 +2056,7 @@ gpioh: gpio@442b0000 { reg = <0x70000 0x400>; clocks = <&scmi_clk CK_SCMI_GPIOH>; st,bank-name = "GPIOH"; + bootph-all; status = "disabled"; };
@@ -2048,6 +2068,7 @@ gpioi: gpio@442c0000 { reg = <0x80000 0x400>; clocks = <&scmi_clk CK_SCMI_GPIOI>; st,bank-name = "GPIOI"; + bootph-all; status = "disabled"; };
@@ -2059,6 +2080,7 @@ gpioj: gpio@442d0000 { reg = <0x90000 0x400>; clocks = <&scmi_clk CK_SCMI_GPIOJ>; st,bank-name = "GPIOJ"; + bootph-all; status = "disabled"; };
@@ -2070,6 +2092,7 @@ gpiok: gpio@442e0000 { reg = <0xa0000 0x400>; clocks = <&scmi_clk CK_SCMI_GPIOK>; st,bank-name = "GPIOK"; + bootph-all; status = "disabled"; }; };
@@ -2092,6 +2115,7 @@ pinctrl_z: pinctrl@46200000 { interrupt-parent = <&exti1>; st,syscfg = <&exti1 0x60 0xff>; pins-are-numbered; + bootph-all; gpioz: gpio@46200000 { gpio-controller;
@@ -2102,6 +2126,7 @@ gpioz: gpio@46200000 { clocks = <&scmi_clk CK_SCMI_GPIOZ>; st,bank-name = "GPIOZ"; st,bank-ioport = <11>; + bootph-all; status = "disabled"; }; };
diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/st/stm32mp255.dtsi
index 7a598f53a2a0..7b2e07613030 100644
--- a/arch/arm64/boot/dts/st/stm32mp255.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi@@ -21,6 +21,7 @@ lvds: lvds@48060000 { resets = <&rcc LVDS_R>; access-controllers = <&rifsc 84>; power-domains = <&CLUSTER_PD>; + bootph-all; status = "disabled"; };
@@ -40,4 +41,4 @@ venc: venc@480e0000 { clocks = <&rcc CK_BUS_VENC>; access-controllers = <&rifsc 90>; }; -};
\ No newline at end of file +};
diff --git a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts
index e718d888ce21..69bac9e719d7 100644
--- a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts
+++ b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts@@ -130,7 +130,18 @@ &usart2 { pinctrl-0 = <&usart2_pins_a>; pinctrl-1 = <&usart2_idle_pins_a>; pinctrl-2 = <&usart2_sleep_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status = "okay"; }; + +&usart2_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +};
diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
index 6e165073f732..307b9692b00a 100644
--- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
+++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts@@ -477,11 +477,22 @@ &usart2 { pinctrl-0 = <&usart2_pins_a>; pinctrl-1 = <&usart2_idle_pins_a>; pinctrl-2 = <&usart2_sleep_pins_a>; + bootph-all; /delete-property/dmas; /delete-property/dma-names; status = "okay"; }; +&usart2_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &usart6 { pinctrl-names = "default", "idle", "sleep"; pinctrl-0 = <&usart6_pins_a>;
--
2.43.0