[PATCH v3 3/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics h7 boards
From: Patrice Chotard <patrice.chotard@foss.st.com>
Date: 2026-01-08 17:16:09
Also in:
linux-arm-kernel, lkml
Subsystem:
arm/stm32 architecture, the rest · Maintainers:
Maxime Coquelin, Alexandre Torgue, Linus Torvalds
The bootph-all flag was introduced in dt-schema (dtschema/schemas/bootph.yaml) to define node usage across different boot phases. To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be present in all boot stages, so add missing bootph-all phase flag to these nodes to support SD boot. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> --- arch/arm/boot/dts/st/stm32h743.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/st/stm32h743.dtsi b/arch/arm/boot/dts/st/stm32h743.dtsi
index 2f19cfbc57ad..790e4558c905 100644
--- a/arch/arm/boot/dts/st/stm32h743.dtsi
+++ b/arch/arm/boot/dts/st/stm32h743.dtsi@@ -50,22 +50,26 @@ / { #size-cells = <1>; clocks { + bootph-all; clk_hse: clk-hse { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; + bootph-all; }; clk_lse: clk-lse { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; + bootph-all; }; clk_i2s: i2s_ckin { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; + bootph-all; }; };
@@ -75,6 +79,7 @@ timer5: timer@40000c00 { reg = <0x40000c00 0x400>; interrupts = <50>; clocks = <&rcc TIM5_CK>; + bootph-all; }; lptimer1: timer@40002400 {
@@ -547,11 +552,13 @@ rcc: reset-clock-controller@58024400 { #reset-cells = <1>; clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>; st,syscfg = <&pwrcfg>; + bootph-all; }; pwrcfg: power-config@58024800 { compatible = "st,stm32-power-config", "syscon"; reg = <0x58024800 0x400>; + bootph-all; }; adc_3: adc@58026000 {
@@ -596,6 +603,7 @@ pinctrl: pinctrl@58020000 { ranges = <0 0x58020000 0x3000>; interrupt-parent = <&exti>; st,syscfg = <&syscfg 0x8>; + bootph-all; gpioa: gpio@58020000 { gpio-controller;
@@ -607,6 +615,7 @@ gpioa: gpio@58020000 { #interrupt-cells = <2>; ngpios = <16>; gpio-ranges = <&pinctrl 0 0 16>; + bootph-all; }; gpiob: gpio@58020400 {
@@ -619,6 +628,7 @@ gpiob: gpio@58020400 { #interrupt-cells = <2>; ngpios = <16>; gpio-ranges = <&pinctrl 0 16 16>; + bootph-all; }; gpioc: gpio@58020800 {
@@ -631,6 +641,7 @@ gpioc: gpio@58020800 { #interrupt-cells = <2>; ngpios = <16>; gpio-ranges = <&pinctrl 0 32 16>; + bootph-all; }; gpiod: gpio@58020c00 {
@@ -643,6 +654,7 @@ gpiod: gpio@58020c00 { #interrupt-cells = <2>; ngpios = <16>; gpio-ranges = <&pinctrl 0 48 16>; + bootph-all; }; gpioe: gpio@58021000 {
@@ -655,6 +667,7 @@ gpioe: gpio@58021000 { #interrupt-cells = <2>; ngpios = <16>; gpio-ranges = <&pinctrl 0 64 16>; + bootph-all; }; gpiof: gpio@58021400 {
@@ -667,6 +680,7 @@ gpiof: gpio@58021400 { #interrupt-cells = <2>; ngpios = <16>; gpio-ranges = <&pinctrl 0 80 16>; + bootph-all; }; gpiog: gpio@58021800 {
@@ -679,6 +693,7 @@ gpiog: gpio@58021800 { #interrupt-cells = <2>; ngpios = <16>; gpio-ranges = <&pinctrl 0 96 16>; + bootph-all; }; gpioh: gpio@58021c00 {
@@ -691,6 +706,7 @@ gpioh: gpio@58021c00 { #interrupt-cells = <2>; ngpios = <16>; gpio-ranges = <&pinctrl 0 112 16>; + bootph-all; }; gpioi: gpio@58022000 {
@@ -703,6 +719,7 @@ gpioi: gpio@58022000 { #interrupt-cells = <2>; ngpios = <16>; gpio-ranges = <&pinctrl 0 128 16>; + bootph-all; }; gpioj: gpio@58022400 {
@@ -715,6 +732,7 @@ gpioj: gpio@58022400 { #interrupt-cells = <2>; ngpios = <16>; gpio-ranges = <&pinctrl 0 144 16>; + bootph-all; }; gpiok: gpio@58022800 {
@@ -727,6 +745,7 @@ gpiok: gpio@58022800 { #interrupt-cells = <2>; ngpios = <8>; gpio-ranges = <&pinctrl 0 160 8>; + bootph-all; }; }; };
--
2.43.0