[PATCH v3 4/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics mp13 boards
From: Patrice Chotard <patrice.chotard@foss.st.com>
Date: 2026-01-08 17:16:11
Also in:
linux-arm-kernel, lkml
Subsystem:
arm/stm32 architecture, the rest · Maintainers:
Maxime Coquelin, Alexandre Torgue, Linus Torvalds
The bootph-all flag was introduced in dt-schema (dtschema/schemas/bootph.yaml) to define node usage across different boot phases. To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be present in all boot stages, so add missing bootph-all phase flag to these nodes to support SD boot. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> --- arch/arm/boot/dts/st/stm32mp131.dtsi | 21 +++++++++++++++++++++ arch/arm/boot/dts/st/stm32mp135f-dk.dts | 11 +++++++++++ 2 files changed, 32 insertions(+)
diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi
index fd730aa37c22..26c3b5529582 100644
--- a/arch/arm/boot/dts/st/stm32mp131.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp131.dtsi@@ -35,6 +35,7 @@ optee { compatible = "linaro,optee-tz"; interrupt-parent = <&intc>; interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + bootph-all; }; scmi: scmi {
@@ -42,15 +43,18 @@ scmi: scmi { #address-cells = <1>; #size-cells = <0>; linaro,optee-channel-id = <0>; + bootph-all; scmi_clk: protocol@14 { reg = <0x14>; #clock-cells = <1>; + bootph-all; }; scmi_reset: protocol@16 { reg = <0x16>; #reset-cells = <1>; + bootph-all; }; scmi_voltd: protocol@17 {
@@ -88,6 +92,7 @@ intc: interrupt-controller@a0021000 { psci { compatible = "arm,psci-1.0"; method = "smc"; + bootph-some-ram; }; timer {
@@ -131,6 +136,7 @@ soc { #size-cells = <1>; interrupt-parent = <&intc>; ranges; + bootph-all; timers2: timer@40000000 { #address-cells = <1>;
@@ -791,6 +797,7 @@ rcc: rcc@50000000 { <&scmi_clk CK_SCMI_CSI>, <&scmi_clk CK_SCMI_LSE>, <&scmi_clk CK_SCMI_LSI>; + bootph-all; }; pwr_regulators: pwr@50001000 {
@@ -900,6 +907,7 @@ syscfg: syscon@50020000 { compatible = "st,stm32mp157-syscfg", "syscon"; reg = <0x50020000 0x400>; clocks = <&rcc SYSCFG>; + bootph-all; }; lptimer4: timer@50023000 {
@@ -1003,6 +1011,7 @@ iwdg2: watchdog@5a002000 { clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; clock-names = "pclk", "lsi"; status = "disabled"; + bootph-all; }; rtc: rtc@5c004000 {
@@ -1020,6 +1029,7 @@ bsec: efuse@5c005000 { reg = <0x5c005000 0x400>; #address-cells = <1>; #size-cells = <1>; + bootph-all; part_number_otp: part_number_otp@4 { reg = <0x4 0x2>;
@@ -1646,6 +1656,7 @@ usbphyc: usbphyc@5a006000 { vdda1v8-supply = <&scmi_reg18>; access-controllers = <&etzpc 5>; status = "disabled"; + bootph-all; usbphyc_port0: usb-phy@0 { #phy-cells = <0>;
@@ -1670,6 +1681,7 @@ pinctrl: pinctrl@50002000 { ranges = <0 0x50002000 0x8400>; interrupt-parent = <&exti>; st,syscfg = <&exti 0x60 0xff>; + bootph-all; gpioa: gpio@50002000 { gpio-controller;
@@ -1681,6 +1693,7 @@ gpioa: gpio@50002000 { st,bank-name = "GPIOA"; ngpios = <16>; gpio-ranges = <&pinctrl 0 0 16>; + bootph-all; }; gpiob: gpio@50003000 {
@@ -1693,6 +1706,7 @@ gpiob: gpio@50003000 { st,bank-name = "GPIOB"; ngpios = <16>; gpio-ranges = <&pinctrl 0 16 16>; + bootph-all; }; gpioc: gpio@50004000 {
@@ -1705,6 +1719,7 @@ gpioc: gpio@50004000 { st,bank-name = "GPIOC"; ngpios = <16>; gpio-ranges = <&pinctrl 0 32 16>; + bootph-all; }; gpiod: gpio@50005000 {
@@ -1717,6 +1732,7 @@ gpiod: gpio@50005000 { st,bank-name = "GPIOD"; ngpios = <16>; gpio-ranges = <&pinctrl 0 48 16>; + bootph-all; }; gpioe: gpio@50006000 {
@@ -1729,6 +1745,7 @@ gpioe: gpio@50006000 { st,bank-name = "GPIOE"; ngpios = <16>; gpio-ranges = <&pinctrl 0 64 16>; + bootph-all; }; gpiof: gpio@50007000 {
@@ -1741,6 +1758,7 @@ gpiof: gpio@50007000 { st,bank-name = "GPIOF"; ngpios = <16>; gpio-ranges = <&pinctrl 0 80 16>; + bootph-all; }; gpiog: gpio@50008000 {
@@ -1753,6 +1771,7 @@ gpiog: gpio@50008000 { st,bank-name = "GPIOG"; ngpios = <16>; gpio-ranges = <&pinctrl 0 96 16>; + bootph-all; }; gpioh: gpio@50009000 {
@@ -1765,6 +1784,7 @@ gpioh: gpio@50009000 { st,bank-name = "GPIOH"; ngpios = <15>; gpio-ranges = <&pinctrl 0 112 15>; + bootph-all; }; gpioi: gpio@5000a000 {
@@ -1777,6 +1797,7 @@ gpioi: gpio@5000a000 { st,bank-name = "GPIOI"; ngpios = <8>; gpio-ranges = <&pinctrl 0 128 8>; + bootph-all; }; }; };
diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts
index 9764a6bfa5b4..a05d458c9b37 100644
--- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts
+++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts@@ -517,9 +517,20 @@ &uart4 { pinctrl-2 = <&uart4_idle_pins_a>; /delete-property/dmas; /delete-property/dma-names; + bootph-all; status = "okay"; }; +&uart4_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; + &uart8 { pinctrl-names = "default", "sleep", "idle"; pinctrl-0 = <&uart8_pins_a>;
--
2.43.0