On 9/4/2025 8:01 PM, Konrad Dybcio wrote:

From: Konrad Dybcio <redacted>

The CCI clock has voltage requirements, which need to be described
through an OPP table.

The 1 MHz FAST_PLUS mode requires the CCI core clock runs at 37,5 MHz

Typo: 37.5 MHz> (which is a value common across all SoCs), since it's 
not possible to

reach the required timings with the default 19.2 MHz rate.

Address both issues by introducing an OPP table and using it to vote
for the faster rate.

Signed-off-by: Konrad Dybcio <redacted>
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