[PATCH 5/5] arm64: dts: qcom: sc8280xp: Add OPP table for CCI hosts
From: Konrad Dybcio <konradybcio@kernel.org>
Date: 2025-09-04 14:31:48
Also in:
linux-arm-msm, linux-i2c, lkml
Subsystem:
arm/qualcomm mailing list, arm/qualcomm support, the rest · Maintainers:
Bjorn Andersson, Konrad Dybcio, Linus Torvalds
From: Konrad Dybcio <redacted> The CCI hosts have both frequency and voltage requirements (which happen to be common across instances on a given SoC, at least so far). Express them by introducing an OPP table and linking it to the hosts. Signed-off-by: Konrad Dybcio <redacted> --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 18b5cb441f955f7a91204376e05536b203f3e28b..c396186317d49f411d7162771a358563329a02a4 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi@@ -391,6 +391,15 @@ memory@80000000 { reg = <0x0 0x80000000 0x0 0x0>; }; + cci_opp_table: opp-table-cci { + compatible = "operating-points-v2"; + + opp-37500000 { + opp-hz = /bits/ 64 <37500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + }; + cpu0_opp_table: opp-table-cpu0 { compatible = "operating-points-v2"; opp-shared;
@@ -4181,6 +4190,7 @@ cci0: cci@ac4a000 { "cpas_ahb", "cci"; + operating-points-v2 = <&cci_opp_table>; power-domains = <&camcc TITAN_TOP_GDSC>; pinctrl-0 = <&cci0_default>;
@@ -4222,6 +4232,7 @@ cci1: cci@ac4b000 { "cpas_ahb", "cci"; + operating-points-v2 = <&cci_opp_table>; power-domains = <&camcc TITAN_TOP_GDSC>; pinctrl-0 = <&cci1_default>;
@@ -4262,6 +4273,8 @@ cci2: cci@ac4c000 { "slow_ahb_src", "cpas_ahb", "cci"; + + operating-points-v2 = <&cci_opp_table>; power-domains = <&camcc TITAN_TOP_GDSC>; pinctrl-0 = <&cci2_default>;
@@ -4303,6 +4316,7 @@ cci3: cci@ac4d000 { "cpas_ahb", "cci"; + operating-points-v2 = <&cci_opp_table>; power-domains = <&camcc TITAN_TOP_GDSC>; pinctrl-0 = <&cci3_default>;
--
2.51.0