Re: [PATCH 07/37] clk: renesas: rzg2l: lock around writes to mux register

On 14.09.2023 15:13, Geert Uytterhoeven wrote:

Hi Claudiu,

On Tue, Sep 12, 2023 at 6:52 AM Claudiu [off-list ref] wrote:

quoted

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

SD MUX output (SD0) is further divided by 4 in G2{L, UL}. The divided
clock is SD0_DIV4. SD0_DIV4 is registered with CLK_SET_RATE_PARENT which
means a rate request for it is propagated to the MUX and could reach
rzg2l_cpg_sd_clk_mux_set_parent() concurrently with the users of SD0.
Add proper locking to avoid concurrent access on SD MUX set rate
registers.

Fixes: eaff33646f4cb ("clk: renesas: rzg2l: Add SDHI clk mux support")
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Thanks for your patch!

quoted

--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c

@@ -189,6 +189,7 @@ static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index)
        u32 shift = GET_SHIFT(hwdata->conf);
        const u32 clk_src_266 = 2;
        u32 msk, val, bitmask;
+       unsigned long flags;
        int ret;

        /*

@@ -203,25 +204,27 @@ static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index)
         * the index to value mapping is done by adding 1 to the index.
         */
        bitmask = (GENMASK(GET_WIDTH(hwdata->conf) - 1, 0) << shift) << 16;
+       spin_lock_irqsave(&priv->rmw_lock, flags);
        if (index != clk_src_266) {
                writel(bitmask | ((clk_src_266 + 1) << shift), priv->base + off);

                msk = off ? CPG_CLKSTATUS_SELSDHI1_STS : CPG_CLKSTATUS_SELSDHI0_STS;

-               ret = readl_poll_timeout(priv->base + CPG_CLKSTATUS, val,
-                                        !(val & msk), 100,
-                                        CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US);
-               if (ret) {
-                       dev_err(priv->dev, "failed to switch clk source\n");
-                       return ret;
-               }
+               ret = readl_poll_timeout_atomic(priv->base + CPG_CLKSTATUS, val,
+                                               !(val & msk), 100,

According to the read_poll_timeout_atomic() documentation,
delay_us should be less than ~10us.

I'll update it, thanks for pointing it.

quoted

+                                               CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US);

CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US = 20 ms, which is a long timeout
for an atomic poll.

I'll have to find the the rationale behind the original timeout. It may be
random, experimental or hardware related.

quoted

+               if (ret)
+                       goto unlock;
        }

        writel(bitmask | ((index + 1) << shift), priv->base + off);

-       ret = readl_poll_timeout(priv->base + CPG_CLKSTATUS, val,
-                                !(val & msk), 100,
-                                CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US);
+       ret = readl_poll_timeout_atomic(priv->base + CPG_CLKSTATUS, val,
+                                       !(val & msk), 100,
+                                       CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US);

Likewise.

quoted

+unlock:
+       spin_unlock_irqrestore(&priv->rmw_lock, flags);
+
        if (ret)
                dev_err(priv->dev, "failed to switch clk source\n");

The rest LGTM.

Gr{oetje,eeting}s,

                        Geert