Hi Conor,
On Mon, Nov 8, 2021 at 4:07 PM [off-list ref] wrote:
From: Conor Dooley <conor.dooley@microchip.com>
Add device tree bindings for the {q,}spi controller on
the Microchip PolarFire SoC.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Thanks for your patch!
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--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/microchip,mpfs-spi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip MPFS {Q,}SPI Controller Device Tree Bindings
+
+maintainers:
+ - Conor Dooley <conor.dooley@microchip.com>
+
+description: |
+ This {Q,}SPI controller is found on the Microchip PolarFire SoC.
+
+allOf:
+ - $ref: "spi-controller.yaml#"
+
+properties:
+ compatible:
+ enum:
+ - microchip,mpfs-spi
+ - microsemi,ms-pf-mss-spi
+ - microchip,mpfs-qspi
+ - microsemi,ms-pf-mss-qspi
Same comment as before: what are the ms-pf-mss entries?
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+examples:
+ - |
+ #include "dt-bindings/clock/microchip,mpfs-clock.h"
+ #include "dt-bindings/interrupt-controller/microchip,mpfs-plic.h"
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
Please drop these two...
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+ spi0: spi@20108000 {
+ compatible = "microchip,mpfs-spi";
+ reg = <0x0 0x20108000 0x0 0x1000>;
... and the zeros here.
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+ clocks = <&clkcfg CLK_SPI0>;
+ interrupt-parent = <&plic>;
+ interrupts = <PLIC_INT_SPI0>;
+ spi-max-frequency = <25000000>;
+ num-cs = <8>;
+ status = "disabled";
Please drop this.
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Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds