[PATCH v2 08/11] arm64: dts: renesas: r9a07g044: Add USB2.0 phy and host support
From: Biju Das <biju.das.jz@bp.renesas.com>
Date: 2021-06-21 09:40:16
Also in:
linux-renesas-soc
Subsystem:
arm/risc-v/renesas architecture, the rest · Maintainers:
Geert Uytterhoeven, Magnus Damm, Linus Torvalds
Add USB2.0 phy and host support to SoC DT. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 100 +++++++++++++++++++++ 1 file changed, 100 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 397e3b182c02..ae71404c6238 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi@@ -236,6 +236,106 @@ <0x0 0x11940000 0 0x60000>; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; }; + + usbphyctrl: usbphyctrl@11c40000 { + compatible = "renesas,r9a07g044-usbphyctrl", + "renesas,rzg2l-usbphyctrl"; + reg = <0 0x11c40000 0 0x10000>; + clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>; + resets = <&cpg R9A07G044_USB_PCLK>; + power-domains = <&cpg>; + #phy-cells = <1>; + }; + + ohci0: usb@11c50000 { + compatible = "renesas,r9a07g044-ohci", + "generic-ohci"; + reg = <0 0x11c50000 0 0x100>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, + <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>; + resets = <&cpg R9A07G044_USB_PCLK>, + <&cpg R9A07G044_USB_U2H0_HCLK>; + phys = <&usbphyctrl 0>, <&usb2_phy0 1>; + phy-names = "usbphyctrl", "usb"; + power-domains = <&cpg>; + status = "disabled"; + }; + + ohci1: usb@11c70000 { + compatible = "renesas,r9a07g044-ohci", + "generic-ohci"; + reg = <0 0x11c70000 0 0x100>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, + <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>; + resets = <&cpg R9A07G044_USB_PCLK>, + <&cpg R9A07G044_USB_U2H1_HCLK>; + phys = <&usbphyctrl 1>, <&usb2_phy1 1>; + phy-names = "usbphyctrl", "usb"; + power-domains = <&cpg>; + status = "disabled"; + }; + + ehci0: usb@11c50100 { + compatible = "renesas,r9a07g044-ehci", + "generic-ehci"; + reg = <0 0x11c50100 0 0x100>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, + <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>; + resets = <&cpg R9A07G044_USB_PCLK>, + <&cpg R9A07G044_USB_U2H0_HCLK>; + phys = <&usbphyctrl 0>, <&usb2_phy0 2>; + phy-names = "usbphyctrl", "usb"; + companion = <&ohci0>; + power-domains = <&cpg>; + status = "disabled"; + }; + + ehci1: usb@11c70100 { + compatible = "renesas,r9a07g044-ehci", + "generic-ehci"; + reg = <0 0x11c70100 0 0x100>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, + <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>; + resets = <&cpg R9A07G044_USB_PCLK>, + <&cpg R9A07G044_USB_U2H1_HCLK>; + phys = <&usbphyctrl 1>, <&usb2_phy1 2>; + phy-names = "usbphyctrl", "usb"; + companion = <&ohci1>; + power-domains = <&cpg>; + status = "disabled"; + }; + + usb2_phy0: usb-phy@11c50200 { + compatible = "renesas,usb2-phy-r9a07g044", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0x11c50200 0 0x700>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, + <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>; + resets = <&cpg R9A07G044_USB_PCLK>, + <&cpg R9A07G044_USB_U2H0_HCLK>; + #phy-cells = <1>; + power-domains = <&cpg>; + status = "disabled"; + }; + + usb2_phy1: usb-phy@11c70200 { + compatible = "renesas,usb2-phy-r9a07g044", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0x11c70200 0 0x700>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, + <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>; + resets = <&cpg R9A07G044_USB_PCLK>, + <&cpg R9A07G044_USB_U2H1_HCLK>; + #phy-cells = <1>; + power-domains = <&cpg>; + status = "disabled"; + }; }; timer {
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2.17.1