On Tue, Mar 16, 2021 at 12:00:52AM +0530, Pratyush Yadav wrote:

+Cc mtd list

Hi,

On 15/03/21 05:45PM, Kuldeep Singh wrote:

quoted

Convert the Freescale DSPI binding to DT schema format using json-schema.

Signed-off-by: Kuldeep Singh <redacted>
---
Hi Rob,
This patch is checked with following commands with no warnings observed.
make distclean; make allmodconfig;
make dt_binding_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/spi/fsl,spi-fsl-dspi.yaml;
make dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/spi/fsl,spi-fsl-dspi.yaml

When I add the "fsl,spi-cs-sck-delay" property under the flash@0 node in 
the example and run dt_binding_check, I see the below error:

  /home/pratyush/src/linux/Documentation/devicetree/bindings/spi/fsl,spi-fsl-dspi.example.dt.yaml: flash@0: 'fsl,spi-cs-sck-delay' does not match any of the regexes: '^partition@', 'pinctrl-[0-9]+'
     From schema: /home/pratyush/src/lin/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml

I am trying to solve a similar problem for the Cadence QSPI controller 
binding and I wonder what the best solution for this is. The obvious one 
would be to add these properties to jedec,spi-nor.yaml. I haven't 
managed to come up with any other solution to this problem.

Rob, all, any suggestions on how to best model this?

I'm aware of the issue, but I don't have a solution for this situation. 
It's a problem anywhere we have a parent or bus binding defining 
properties for child nodes. For now, I'd just avoid it in the examples 
and we'll figure out how to deal with actual dts files later.

For this one in particular, CS to clock timing isn't any FSL or 
controller specific, but is device specific. So this probably should 
have been a generic spi bus property (if not implicit). That's somewhat 
easier to work-around than potentially adding controller specific 
properties to every slave device schema.

Rob