Thread (105 messages) 105 messages, 10 authors, 2020-12-22

Re: [PATCH v1 00/30] Introduce core voltage scaling for NVIDIA Tegra20/30 SoCs

From: Dmitry Osipenko <digetx@gmail.com>
Date: 2020-11-05 15:22:21
Also in: dri-devel, linux-media, linux-mmc, linux-pwm, linux-samsung-soc, linux-tegra, linux-usb, lkml

05.11.2020 12:45, Ulf Hansson пишет:
...
I need some more time to review this, but just a quick check found a
few potential issues...
Thank you for starting the review! I'm pretty sure it will take a couple
revisions until all the questions will be resolved :)
The "core-supply", that you specify as a regulator for each
controller's device node, is not the way we describe power domains.
Instead, it seems like you should register a power-domain provider
(with the help of genpd) and implement the ->set_performance_state()
callback for it. Each device node should then be hooked up to this
power-domain, rather than to a "core-supply". For DT bindings, please
have a look at Documentation/devicetree/bindings/power/power-domain.yaml
and Documentation/devicetree/bindings/power/power_domain.txt.

In regards to the "sync state" problem (preventing to change
performance states until all consumers have been attached), this can
then be managed by the genpd provider driver instead.
I'll need to take a closer look at GENPD, thank you for the suggestion.

Sounds like a software GENPD driver which manages clocks and voltages
could be a good idea, but it also could be an unnecessary
over-engineering. Let's see..
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