[PATCH v1 05/30] dt-binding: usb: ci-hdrc-usb2: Document OPP and voltage regulator properties
From: Dmitry Osipenko <digetx@gmail.com>
Date: 2020-11-04 23:50:03
Also in:
dri-devel, linux-media, linux-mmc, linux-pwm, linux-samsung-soc, linux-tegra, linux-usb, lkml
Subsystem:
open firmware and flattened device tree bindings, the rest, usb subsystem · Maintainers:
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds, Greg Kroah-Hartman
Document new OPP table and NVIDIA Tegra-specific voltage regulator properties. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt
index a5c5db6a0b2d..f02a98201062 100644
--- a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt
+++ b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt@@ -90,6 +90,7 @@ Optional properties: case, the "idle" state needs to pull down the data and strobe pin and the "active" state needs to pull up the strobe pin. - pinctrl-n: alternate pin modes +- operating-points-v2: See ../bindings/opp/opp.txt for details. i.mx specific properties - fsl,usbmisc: phandler of non-core register device, with one
@@ -110,6 +111,9 @@ i.mx specific properties The range is from 0x0 to 0xf, the default value is 0x3. Details can refer to TXVREFTUNE0 bits of USBNC_n_PHY_CFG1. +Tegra specific properties +- core-supply: phandle of voltage regulator of the SoC "core" power domain + Example: usb@f7ed0000 {
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2.27.0