On Wed, 17 Jul 2019 at 14:56, Lukasz Luba [off-list ref] wrote:

On 7/17/19 1:11 PM, Krzysztof Kozlowski wrote:

quoted

On Wed, 17 Jul 2019 at 13:06, Lukasz Luba [off-list ref] wrote:

quoted

On 7/17/19 12:45 PM, Krzysztof Kozlowski wrote:

quoted

On Wed, 17 Jul 2019 at 12:39, Lukasz Luba [off-list ref] wrote:

quoted

quoted

quoted

    &bus_fsys {
           devfreq = <&bus_wcore>;
+       assigned-clocks = <&clock CLK_MOUT_ACLK200_FSYS>,
+                         <&clock CLK_DOUT_ACLK200_FSYS>,
+                         <&clock CLK_FOUT_DPLL>;
+       assigned-clock-parents = <&clock CLK_MOUT_SCLK_DPLL>;
+       assigned-clock-rates = <0>, <240000000>,<1200000000>;

Here and in all other patches:
I am not entirely sure that this should be here. It looks like
property of the SoC. Do we expect that buses will be configured to
different clock rates between different boards?

This is the board file for Exynos5420/5422/5800 which enables buses.
Thus, I have change them here. Patch 49/50 adds these buses to
Exynos5800 (Peach Pi). In Exynos5420 there is no clock tree for
bus_isp266. The parents for different devices could be also different.
It is because i.e. in 5420 there is 2 bit in the WCORE 1st mux while in
5422 there is 3 bits (6 parents possible).
That's why I have picked exynos5422-odroid-core.dtsi to reference
the bus devices and pinned them into proper parent and changed rate.
When you check patch 49/50 for 5800 not all the parents are the same.

(1) I could create a dedicated files like: exynos5422-bus.dtsi,
exynos5420-bus.dtsi, exynos5800-bus.dtsi which would include some
base file with the basic &bus_X and set the right parent, rate.
Then these files would be included into proper board file like:
exynos5800-peach-pi.dts.
Is this something that you would like to see?

I see now. Are there any differences in all these properties between
Peach Pi and Odroids? Both of them are using exynos5800.dtsi so that
could be a place for all clock assignments.

Best regards,
Krzysztof