On 5/7/19 9:36 AM, Chanwoo Choi wrote:

Hi Lukasz,

On 19. 5. 7. 오전 12:11, Lukasz Luba wrote:

quoted

Add new table rate for BPLL for Exynos5422 SoC supporting Dynamic Memory
Controller frequencies for driver's DRAM timings.

Signed-off-by: Lukasz Luba <redacted>
---
  drivers/clk/samsung/clk-exynos5420.c | 17 ++++++++++++++++-
  1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index af62b6d..23c60a5 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c

@@ -1335,6 +1335,17 @@ static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __ini
  	PLL_35XX_RATE(24 * MHZ, 200000000,  200, 3, 3),
  };
  
+static const struct samsung_pll_rate_table exynos5422_bpll_rate_table[] = {
+	PLL_35XX_RATE(24 * MHZ, 825000000, 275, 4, 1),
+	PLL_35XX_RATE(24 * MHZ, 728000000, 182, 3, 1),
+	PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1),
+	PLL_35XX_RATE(24 * MHZ, 543000000, 181, 2, 2),
+	PLL_35XX_RATE(24 * MHZ, 413000000, 413, 6, 2),
+	PLL_35XX_RATE(24 * MHZ, 275000000, 275, 3, 3),
+	PLL_35XX_RATE(24 * MHZ, 206000000, 206, 3, 3),
+	PLL_35XX_RATE(24 * MHZ, 165000000, 110, 2, 3),
+};
+
  static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = {
  	PLL_36XX_RATE(24 * MHZ, 600000000U, 100, 2, 1, 0),
  	PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),

@@ -1477,9 +1488,13 @@ static void __init exynos5x_clk_init(struct device_node *np,
  		exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
  		exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl;
  		exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
-		exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
  	}
  
+	if (soc == EXYNOS5420)
+		exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
+	else
+		exynos5x_plls[bpll].rate_table = exynos5422_bpll_rate_table;
+
  	samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),
  					reg_base);
  	samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks,

Acked-by: Chanwoo Choi <cw00.choi@samsung.com>

Thank you, added to the patch.

Regards,
Lukasz