Re: [PATCH v4 02/11] clk: sunxi-ng: a64: Add max. rate constraint to video PLLs
From: Maxime Ripard <hidden>
Date: 2018-09-05 07:16:51
Also in:
dri-devel, linux-arm-kernel, linux-clk, lkml
On Tue, Sep 04, 2018 at 12:40:44PM +0800, Icenowy Zheng wrote:
Video PLLs on A64 can be set to higher rate that it is actually supported by HW. Limit maximum rate to 1008 MHz. This is the maximum allowed rate by BSP clock driver. Interestengly, user manual specifies maximum frequency to be 600 MHz. Historically, this data was wrong in some user manuals for other SoCs, so more faith is put in BSP clock driver. Signed-off-by: Icenowy Zheng <redacted>
Applied, thanks! Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com