Hi Chris,

On Tue, Aug 28, 2018 at 7:18 PM Chris Brandt [off-list ref] wrote:

Since my config for RZ/A2 does not set CONFIG_RESET_CONTROLLER, none of
the reset code is built and cpg_mssr_reset_controller_register() just
ends up being an empty function.

Let's try shmobile_defconfig instead :-)

Seriously, you do have to prevent registering the reset controller when
running on RZ/A2 (based on cpg_mssr_info.stbyctrl or some other indicator).

So basically my only change at this point is to make DTS and the module
clock table use "36" instead of "306".

Are you OK with the idea of adding a macro ("STBCR_ID") in
include/dt-bindings/clock/renesas-cpg-mssr.h?


DTS:
--------------------
        ostm0: timer@e803b000 {
                compatible = "renesas,r7s9210-ostm", "renesas,ostm";
                reg = <0xe803b000 0x30>;
                interrupts = <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>;
                clocks = <&cpg CPG_MOD STBCR_ID(36)>;
                clock-names = "ostm0";
                power-domains = <&cpg>;
                status = "disabled";
        };

When running on RZ/A2, I'd use a different pack function in
cpg_mssr_clk_src_twocell_get() instead, so you can just write:

    clock = <&cpg CPG_MOD 36>;

r7s9210-cpg-mssr.c:
--------------------
static const struct mssr_mod_clk r7s9210_mod_clks[] __initconst = {
        DEF_MOD("ostm0",        STBCR_ID(36),   R7S9210_CLK_P1C),
        DEF_MOD("ostm1",        STBCR_ID(35),   R7S9210_CLK_P1C),
        DEF_MOD("ostm2",        STBCR_ID(34),   R7S9210_CLK_P1C),

... and a different DEF_MOD() macro here, so you can just write:

    DEF_MOD("ostm0",        36,   R7S9210_CLK_P1C),

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds