Hi Geert,

On Tuesday, August 28, 2018, Geert Uytterhoeven wrote:

Seriously, you do have to prevent registering the reset controller when
running on RZ/A2 (based on cpg_mssr_info.stbyctrl or some other indicator).

OK. Since the reset controller registration is the last thing done 
cpg_mssr_probe, I'll just return.

+	if (info->stbyctrl)
+		return 0;
+
	error = cpg_mssr_reset_controller_register(priv);
	if (error)
		return error;

	return 0;
}

When running on RZ/A2, I'd use a different pack function in
cpg_mssr_clk_src_twocell_get() instead, so you can just write:

    clock = <&cpg CPG_MOD 36>;

quoted

r7s9210-cpg-mssr.c:
--------------------
static const struct mssr_mod_clk r7s9210_mod_clks[] __initconst = {
        DEF_MOD("ostm0",        STBCR_ID(36),   R7S9210_CLK_P1C),
        DEF_MOD("ostm1",        STBCR_ID(35),   R7S9210_CLK_P1C),
        DEF_MOD("ostm2",        STBCR_ID(34),   R7S9210_CLK_P1C),

... and a different DEF_MOD() macro here, so you can just write:

    DEF_MOD("ostm0",        36,   R7S9210_CLK_P1C),

OK. I will do that instead.


Thank you,
Chris