On Mon, Dec 04, 2017 at 10:17:47AM +0100, Geert Uytterhoeven wrote:

On Thu, Nov 30, 2017 at 2:29 PM, Geert Uytterhoeven
[off-list ref] wrote:

quoted

Certain EEPROMS have a size that is larger than the number of address
bytes would allow, and store the MSB of the address in bit 3 of the
instruction byte.

This can be described in platform data using EE_INSTR_BIT3_IS_ADDR, or
in DT using the obsolete legacy "at25,addr-mode" property.
But currently there exists no non-deprecated way to describe this in DT.

Hence extend the existing "address-width" DT property to allow
specifying 9, 17, or 25 address bits, and enable support for that in the
driver.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
EEPROMs using 9 address bits are common (e.g. M95040, 25AA040/25LC040).
Do EEPROMs using 17 or 25 address bits, as mentioned in
include/linux/spi/eeprom.h, really exist?
Or should we just limit it to a single odd value (9 bits)?

At least for the real Atmel parts, only the AT25040 part uses odd (8 +
1 bit) addressing.

Seems like we should have a specific compatible for it.

AT25M01 uses 3-byte addressing (it needs 17 bits).

Do you need to know it is 17-bit vs. 24-bits? I'm guessing not as the 
unused bits are probably don't care.

Rob