On 2017-08-02 11:31, Archit Taneja wrote:

On 07/19/2017 05:17 PM, Abhishek Sahu wrote:

quoted

Each NAND page consist of multiple codewords. Following is
sequence for NAND page write according to hardware guide.

1. Program Power-up configuration, page row, page column
    address and flash configuration registers.
2. Write NAND_FLASH_CMD followed by NANC_EXEC_CMD for each
    codeword.
3. Read NAND_FLASH_STATUS for each codeword.

The step 1 should be done once for each page and step 2,3 should
be done for each codeword.

Currently, all the 3 steps are being done for each codeword which
is wrong. Now this patch reorganizes page write functions to
configure page specific register once and per codeword specific
registers for each NAND ECC step.

Thanks for fixing this. I'm assuming this has been tested on IPQ806x
too.

  Thanks Archit for reviewing the patches.

  Yes. I have tested this in IPQ8064 AP148 board with mtd tests after
  applying the ADM DMA patch from list.

Reviewed-by: Archit Taneja <redacted>

quoted

Signed-off-by: Abhishek Sahu <redacted>
---
  drivers/mtd/nand/qcom_nandc.c | 32 ++++++++++++++++++++------------
  1 file changed, 20 insertions(+), 12 deletions(-)

diff --git a/drivers/mtd/nand/qcom_nandc.c 

b/drivers/mtd/nand/qcom_nandc.c
index 27ea594..5b71478 100644

--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c

@@ -638,15 +638,24 @@ static void 

config_nand_single_cw_page_read(struct qcom_nand_controller *nandc)
  	config_nand_cw_read(nandc);
  }