[PATCH] arm64: dts: mediatek: mt8188-geralt: Add MT6319 PMIC
From: Chen-Yu Tsai <wenst@chromium.org>
Date: 2026-07-07 10:44:43
Also in:
linux-devicetree, linux-mediatek, lkml
Subsystem:
arm/mediatek soc support, the rest · Maintainers:
Matthias Brugger, AngeloGioacchino Del Regno, Linus Torvalds
The Geralt design uses a MT6319 PMIC to power the big cores and LPDDR4X DRAM. Add a device node for it and hook up all the supplies. This change requires a firmware fix for the SPMI bus to read back correctly. The required firmware version is 15842.175.0. This is included in ChromeOS releases R150-16700.22.0 (available in Beta channel as of writing or stable channel in mid-July) or R151-16721.0.0 and later. Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> --- .../boot/dts/mediatek/mt8188-geralt.dtsi | 66 +++++++++++++++++++ 1 file changed, 66 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi b/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi
index f382f90c48f5..fea52c377d88 100644
--- a/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi@@ -4,6 +4,8 @@ */ /dts-v1/; #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/spmi/spmi.h> + #include "mt8188.dtsi" #include "mt6359.dtsi"
@@ -241,6 +243,14 @@ &cpu5 { cpu-supply = <&mt6359_vcore_buck_reg>; }; +&cpu6 { + cpu-supply = <&mt6319_buck1>; +}; + +&cpu7 { + cpu-supply = <&mt6319_buck1>; +}; + /* * Geralt is the reference design and doesn't have target TDP. * Ciri is (currently) the only device following Geralt, and its
@@ -1156,6 +1166,14 @@ pins-bus { }; }; + spmi_pins: spmi-pins { + pins-bus { + pinmux = <PINMUX_GPIO175__FUNC_B0_SPMI_M_SCL>, + <PINMUX_GPIO176__FUNC_B0_SPMI_M_SDA>; + bias-disable; + }; + }; + uart0_pins: uart0-pins { pins-bus { pinmux = <PINMUX_GPIO31__FUNC_O_UTXD0>,
@@ -1267,6 +1285,54 @@ &spi2 { status = "okay"; }; +&spmi { + pinctrl-names = "default"; + pinctrl-0 = <&spmi_pins>; + #address-cells = <2>; + #size-cells = <0>; + status = "okay"; + + pmic@6 { + compatible = "mediatek,mt6319-regulator", "mediatek,mt6315-regulator"; + reg = <0x6 SPMI_USID>; + pvdd1-supply = <&pp4200_s5>; + pvdd2-supply = <&pp4200_s5>; + pvdd3-supply = <&pp4200_s5>; + pvdd4-supply = <&pp4200_s5>; + + regulators { + mt6319_buck1: vbuck1 { + regulator-name = "ppvar_dvdd_proc_bc"; + regulator-min-microvolt = <520000>; + regulator-max-microvolt = <1155000>; + regulator-enable-ramp-delay = <256>; + regulator-allowed-modes = <0 1 2>; + regulator-always-on; + }; + + /* vbuck2 is ganged with vbuck1 */ + + mt6319_buck3: vbuck3 { + regulator-name = "pp1125_emi_vdd2"; + regulator-min-microvolt = <1060000>; + regulator-max-microvolt = <1170000>; + regulator-enable-ramp-delay = <256>; + regulator-allowed-modes = <0 1 2>; + regulator-always-on; + }; + + mt6319_buck4: vbuck4 { + regulator-name = "pp0600_emi_vddq"; + regulator-min-microvolt = <570000>; + regulator-max-microvolt = <650000>; + regulator-enable-ramp-delay = <256>; + regulator-allowed-modes = <0 1 2>; + regulator-always-on; + }; + }; + }; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>;
--
2.55.0.rc2.803.g1fd1e6609c-goog