On Mon, Jan 19, 2026 at 06:02:26PM +0800, Sherry Sun wrote:

quoted

Update the fsl,imx6q-pcie.yaml to include the reset-gpios property in
the Root Port node.

There is already 'reset-gpios' property defined for PERST# in
pci-bus-common.yaml, so use that property instead of 'reset-gpio' in
this file, for backward compatibility, do not remove the existing
property in the bridge node, but mark them as 'deprecated' instead.

Update fsl,imx6q-pcie.yaml to include the standard reset-gpios property for
the Root Port node.

The reset-gpios property is already defined in pci-bus-common.yaml for
PERST#, so use it instead of the local reset-gpio property. Keep the existing
reset-gpio property in the bridge node for backward compatibility, but mark it
as deprecated.

Hi Frank, ok, will improve the commit message in V2, thanks!

Best Regards
Sherry

Frank

quoted

Signed-off-by: Sherry Sun <redacted>
---
 .../bindings/pci/fsl,imx6q-pcie.yaml          | 29 +++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml

b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
index 12a01f7a5744..74156b42e7a2 100644

--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml

@@ -59,9 +59,12 @@ properties:
       - const: dma

   reset-gpio:
+    deprecated: true
     description: Should specify the GPIO for controlling the PCI bus device
       reset signal. It's not polarity aware and defaults to active-low reset
       sequence (L=reset state, H=operation state) (optional required).
+      This property is deprecated, instead of referencing this property from

the

quoted

+      host bridge node, use the reset-gpios property from the root port

node.

quoted

   reset-gpio-active-high:
     description: If present then the reset sequence using the GPIO @@
-69,6 +72,18 @@ properties:
       L=operation state) (optional required).
     type: boolean

+  pcie@0:
+    description:
+      Describe the i.MX6 PCIe Root Port.
+    type: object
+    $ref: /schemas/pci/pci-pci-bridge.yaml#
+
+    properties:
+      reg:
+        maxItems: 1
+
+    unevaluatedProperties: false
+
 required:
   - compatible
   - reg

@@ -229,6 +244,7 @@ unevaluatedProperties: false
 examples:
   - |
     #include <dt-bindings/clock/imx6qdl-clock.h>
+    #include <dt-bindings/gpio/gpio.h>
     #include <dt-bindings/interrupt-controller/arm-gic.h>

     pcie: pcie@1ffc000 {

@@ -255,5 +271,18 @@ examples:
                 <&clks IMX6QDL_CLK_LVDS1_GATE>,
                 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
         clock-names = "pcie", "pcie_bus", "pcie_phy";
+
+        pcie_port0: pcie@0 {
+            compatible = "pciclass,0604";
+            device_type = "pci";
+            reg = <0x0 0x0 0x0 0x0 0x0>;
+            bus-range = <0x01 0xff>;
+
+            #address-cells = <3>;
+            #size-cells = <2>;
+            ranges;
+
+            reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
+        };
     };
 ...
--

2.37.1