[PATCH 09/10] arm64: dts: imx8dxl/qm/qxp: Add Root Port nodes and move PERST property to Root Port node
From: Sherry Sun <hidden>
Date: 2026-01-19 10:04:36
Also in:
imx, linux-devicetree, linux-pci, lkml
Subsystem:
arm/freescale imx / mxc arm architecture, the rest · Maintainers:
Frank Li, Sascha Hauer, Linus Torvalds
Since describing the PCIe PERST# property under Host Bridge node is now deprecated, it is recommended to add it to the Root Port node, so creating the Root Port nodes and move the reset-gpios property. Signed-off-by: Sherry Sun <redacted> --- .../boot/dts/freescale/imx8-ss-hsio.dtsi | 11 ++++++++++ arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 5 ++++- arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 10 +++++++-- .../boot/dts/freescale/imx8qm-ss-hsio.dtsi | 22 +++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 5 ++++- 5 files changed, 49 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi
index 469de8b536b5..009990b2e559 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi@@ -78,6 +78,17 @@ pcieb: pcie@5f010000 { power-domains = <&pd IMX_SC_R_PCIE_B>; fsl,max-link-speed = <3>; status = "disabled"; + + pcieb_port0: pcie@0 { + compatible = "pciclass,0604"; + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcieb_ep: pcie-ep@5f010000 {
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
index 5c68d33e19f2..63a655399888 100644
--- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts@@ -651,7 +651,6 @@ &pcie0 { phy-names = "pcie-phy"; pinctrl-0 = <&pinctrl_pcieb>; pinctrl-names = "default"; - reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; vpcie-supply = <®_pcieb>; vpcie3v3aux-supply = <®_pcieb>; status = "okay";
@@ -667,6 +666,10 @@ &pcie0_ep { status = "disabled"; }; +&pcieb_port0 { + reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; +}; + &sai0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai0>;
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
index dadc136aec6e..f57d2391b0ed 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts@@ -802,22 +802,28 @@ &pciea { phy-names = "pcie-phy"; pinctrl-0 = <&pinctrl_pciea>; pinctrl-names = "default"; - reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; vpcie-supply = <®_pciea>; vpcie3v3aux-supply = <®_pciea>; supports-clkreq; status = "okay"; }; +&pciea_port0 { + reset-gpios = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>; +}; + &pcieb { phys = <&hsio_phy 1 PHY_TYPE_PCIE 1>; phy-names = "pcie-phy"; pinctrl-0 = <&pinctrl_pcieb>; pinctrl-names = "default"; - reset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>; status = "disabled"; }; +&pcieb_port0 { + reset-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>; +}; + &qm_pwm_lvds0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm_lvds0>;
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi
index bd6e0aa27efe..48c29c2cfe8b 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi@@ -40,6 +40,17 @@ pcie0: pciea: pcie@5f000000 { power-domains = <&pd IMX_SC_R_PCIE_A>; fsl,max-link-speed = <3>; status = "disabled"; + + pciea_port0: pcie@0 { + compatible = "pciclass,0604"; + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_ep: pciea_ep: pcie-ep@5f000000 {
@@ -90,6 +101,17 @@ pcie1: pcieb: pcie@5f010000 { power-domains = <&pd IMX_SC_R_PCIE_B>; fsl,max-link-speed = <3>; status = "disabled"; + + pcieb_port0: pcie@0 { + compatible = "pciclass,0604"; + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; sata: sata@5f020000 {
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
index 40a0bc9f4e84..fdd9009a2a7e 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts@@ -722,7 +722,6 @@ &pcie0 { phy-names = "pcie-phy"; pinctrl-0 = <&pinctrl_pcieb>; pinctrl-names = "default"; - reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; vpcie-supply = <®_pcieb>; vpcie3v3aux-supply = <®_pcieb>; supports-clkreq;
@@ -738,6 +737,10 @@ &pcie0_ep { status = "disabled"; }; +&pcieb_port0 { + reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; +}; + &scu_key { status = "okay"; };
--
2.37.1