[PATCH 08/10] arm64: dts: imx8mq: Add Root Port nodes and move PERST property to Root Port node
From: Sherry Sun <hidden>
Date: 2026-01-19 10:04:31
Also in:
imx, linux-devicetree, linux-pci, lkml
Subsystem:
arm/freescale imx / mxc arm architecture, the rest · Maintainers:
Frank Li, Sascha Hauer, Linus Torvalds
Since describing the PCIe PERST# property under Host Bridge node is now deprecated, it is recommended to add it to the Root Port node, so creating the Root Port nodes and move the reset-gpios property. Signed-off-by: Sherry Sun <redacted> --- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 10 +++++++-- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 22 ++++++++++++++++++++ 2 files changed, 30 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index d48f901487d4..723b34100a61 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts@@ -369,7 +369,6 @@ mipi_dsi_out: endpoint { &pcie0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie0>; - reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>; clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, <&pcie0_refclk>, <&clk IMX8MQ_CLK_PCIE1_PHY>,
@@ -389,10 +388,13 @@ &pcie0_ep { status = "disabled"; }; +&pcie0_port0 { + reset-gpios = <&gpio5 28 GPIO_ACTIVE_LOW>; +}; + &pcie1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie1>; - reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>; clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, <&pcie0_refclk>, <&clk IMX8MQ_CLK_PCIE2_PHY>,
@@ -414,6 +416,10 @@ &pcie1_ep { status = "disabled"; }; +&pcie1_port0 { + reset-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; +}; + &pgc_gpu { power-supply = <&sw1a_reg>; };
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 607962f807be..de2ba4ee9da6 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi@@ -1768,6 +1768,17 @@ pcie0: pcie@33800000 { assigned-clock-rates = <250000000>, <100000000>, <10000000>; status = "disabled"; + + pcie0_port0: pcie@0 { + compatible = "pciclass,0604"; + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_ep: pcie-ep@33800000 {
@@ -1846,6 +1857,17 @@ pcie1: pcie@33c00000 { assigned-clock-rates = <250000000>, <100000000>, <10000000>; status = "disabled"; + + pcie1_port0: pcie@0 { + compatible = "pciclass,0604"; + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_ep: pcie-ep@33c00000 {
--
2.37.1