Hi Köry,

On Thu Dec 11, 2025 at 5:38 PM CET, Kory Maincent (TI.com) wrote:

The tilcdc hardware does not generate VESA-compliant sync signals. It
aligns the vertical sync (VS) on the second edge of the horizontal sync
(HS) instead of the first edge. To compensate for this hardware
behavior, the driver applies a timing adjustment in mode_fixup().

Previously, this adjustment was conditional based on the simulate_vesa_sync
flag, which was only set when using external encoders. This appears
problematic because:

1. The timing adjustment seems needed for the hardware behavior regardless
   of whether an external encoder is used
2. The external encoder infrastructure is driver-specific and being
   removed due to design issues
3. Boards using tilcdc without bridges (e.g., am335x-evm, am335x-evmsk)
   may not be getting the necessary timing adjustments

Remove the simulate_vesa_sync flag and apply the VESA sync timing
adjustment unconditionally, ensuring consistent behavior across all
configurations. While it's unclear if the previous conditional behavior
was causing actual issues, the unconditional adjustment better reflects
the hardware's characteristics.

Signed-off-by: Kory Maincent (TI.com) <kory.maincent@bootlin.com>

Code looks good. Based on your testing, which covered both boards currently
setting simulate_vesa_sync and boards not setting it:

Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com>

Still it would be good to have this series, and especially this patch,
tested by someone having access to other TI boards.

--
Luca Ceresoli, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com