Subject: Re: [PATCH 00/16] Add support for the Axis ARTPEC-8 SoC

On 06/08/2025 10:22, Pankaj Dubey wrote:

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-----Original Message-----
From: Krzysztof Kozlowski <krzk@kernel.org>
Sent: Monday, July 21, 2025 12:10 PM
To: SeonGu Kang <redacted>; Jesper Nilsson
[off-list ref]; Michael Turquette

[off-list ref];

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Stephen Boyd [off-list ref]; Rob Herring [off-list ref];
Krzysztof Kozlowski [off-list ref]; Conor Dooley
[off-list ref]; Sylwester Nawrocki

[off-list ref];

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Chanwoo Choi [off-list ref]; Alim Akhtar
[off-list ref]; Linus Walleij [off-list ref];
Tomasz Figa [off-list ref]; Catalin Marinas
[off-list ref]; Will Deacon [off-list ref]; Arnd

Bergmann

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[off-list ref]
Cc: kenkim <redacted>; Jongshin Park <redacted>;
GunWoo Kim [off-list ref]; HaGyeong Kim
[off-list ref]; GyoungBo Min [off-list ref];
SungMin Park [off-list ref]; Pankaj Dubey
[off-list ref]; Shradha Todi

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Ravi Patel [off-list ref]; Inbaraj E

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Swathi K S [off-list ref]; Hrishikesh
[off-list ref]; Dongjin Yang [off-list ref];
Sang Min Kim [off-list ref]; linux-

kernel@vger.kernel.org;

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linux-arm-kernel@lists.infradead.org; linux-samsung-

soc@vger.kernel.org;

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linux-arm-kernel@axis.com; linux-clk@vger.kernel.org;
devicetree@vger.kernel.org; linux-gpio@vger.kernel.org;

soc@lists.linux.dev

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Subject: Re: [PATCH 00/16] Add support for the Axis ARTPEC-8 SoC

On 21/07/2025 06:50, SeonGu Kang wrote:

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2025-07-10 (목), 09:07 +0200, Krzysztof Kozlowski:

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On 10/07/2025 02:20, ksk4725@coasia.com wrote:

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From: SeonGu Kang <redacted>

Add basic support for the Axis ARTPEC-8 SoC.
This SoC contains four Cortex-A53 CPUs and other several IPs.

Patches 1 to 10 provide the support for the clock controller, which
is similar to other Samsung SoCs.

You should explain here (and in DTS patches or the bindings) the
hardware, that this is Samsung SoC.

You could also explain the differences from Exynos and proposed
handling of patches (because this is odd)

Also, entire patchset has wrong and incomplete SoBs. Your SoB is
missing everywhere, others have wrong order.

Please read submitting patches first.

This Custom SoC is owned by the Axis (OEM) and manufactured by the
Samsung (ODM). It has standard Samsung specific IP blocks.

It is designed by Samsung. It is Samsung SoC.

Anyway, don't explain to me, but in your patchset.

Hi Krzysztof,

Thank you for your review comments on the ARTPEC-8 platform patches.
I'd like to add more context about the ARTPEC-8 SoC to help clarify its
relationship with Exynos.

Here are the key details about ARTPEC-8:
   - Manufactured by Samsung Foundry
   - SoC architecture is owned by Axis Communications
	- On similar model as Tesla's FSD chip owned by Tesla and
              manufactured and  by Samsung
   - IPs from both Samsung and Axis Communications

Samsung-provided IPs:
  - UART
  - Ethernet (Vendor: Synopsys)
       - Same IP has been integrated as integrated in FSD Chip
  - SDIO
  - SPI
  - HSI2C
  - I2S
  - CMU (Clock Management Unit)
       Follows same CMU HW architecture as Exynos SoC have
  - Pinctrl (GPIO)
  - PCIe (Vendor: Synopsys)
       Though Exynos, FSD, ARTPEC have same DesignWare Controller,
       the glue/wrapper layer around DWC Core has differences across
       these SoCs. All manufactured by Samsung, but differences are there
       in HW design and for different products. For the same reason PCIe

patch

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       refactoring effort is being put by us [1] to streamline single Exynos

driver

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       which can support all Samsung manufactured SoCs having DWC PCIe

controller.

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      [1]: https://protect2.fireeye.com/v1/url?k=8a8233e4-d5190ae8-

8a83b8ab-000babff3563-7bd7c9980190e0e8&q=1&e=2e04cfd4-33cf-4f00-
a970-
7dcbf1d780ec&u=https%3A%2F%2Fpatchwork.ozlabs.org%2Fproject%2Flinu
x-pci%2Fpatch%2F20250625165229.3458-2-shradha.t%40samsung.com%2F

So entire base of the SoC is Samsung.

Yes, if we are saying this based on the core IPs (CMU, Pinctrl) and the fact that
it is manufactured by Samsung.

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Axis-provided IPs:
    - VIP (Image Sensor Processing IP)
    - VPP (Video Post Processing)
    - GPU
    - CDC (Video Encoder)

As part of the upstreaming effort, Samsung and Coasia (DSP) team will

work together

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to upstream basic SoC support and Samsung IPs support.
The Axis team will be the primary maintainer for the ARTPEC-8 SoC

codebase.

Don't know what do you mean by "primary", but I want to be clear: this
classifies as Samsung SoC, so I will be maintaining and overlooking it
just like I maintain and take care about all Samsung SoCs. Otherwise you
will be introducing errors and warnings or, in best case different
style. And this already happened if I did not object!

By "primary" I mean as it is product of Axis, and only Axis will be having access
to this SoCs in future they will be responsible to maintain it and add support for.

Also SAME strict DT compliance profile will be applied. (see more on
that below)

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Given that ARTPEC-8 is a distinct SoC with its own set of IPs, we believe it's

reasonable

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to create a separate directory for it, similar to FSD.

No. It was a mistake for FSD to keep it separate why? Because there is
no single non-Samsung stuff there. I am afraid exactly the same will
happen there.

I am not sure, why you are saying this as a mistake, in case next version of FSD
or ARTPEC is manufactured (ODM) by another vendor in that case, won't it
create problems? 

For example ARTPEC-6/7 (ARM based) have their own directories as "arch/arm/boot/dts/axis/"
These were not Samsung (ODM) manufactures SoCs. 

But ARTPEC-8/9 (ARM64) based SoCs are samsung manufactured. What if the next version say
ARTPEC-10 is not samsung manufactured, so different version of products (SoCs) from
same vendor (OEM), in this case Axis, will have code in separate directories and with different maintainers? 

Based on above list of blocks this should be done like Google is done,
so it goes as subdirectory of samsung (exynos). Can be called axis or
artpec-8.

I will suggest to keep axis, knowing the fact that sooner after artpec-8 patches gets approved and merged
we have plan to upstream artpec-9 (ARM64, Samsung manufactured) as well.

To clarify: Only this SoC, not others which are not Samsung.

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We will remove Samsung and Coasia teams from the maintainers list in v2

and only

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Axis team will be maintainer.

A bit unexpected or rather: just use names of people who WILL be
maintaining it. If this is Jesper and Lars, great. Just don't add
entries just because they are managers.

AFAIK, Jesper will be taking care. 

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Maintainer list for previous generation of Axis chips (ARM based) is already

present,

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so this will be merged into that.

Existing Artpec entry does not have tree mentioned, so if you choose
above, you must not add the tree, since the tree is provided by Samsung SoC.

OK

OTOH, how are you going to add there strict DT compliance? Existing axis
is not following this, but artpec-8, as a Samsung derivative, MUST
FOLLOW strict DT compliance. And this should be clearly marked in
maintainer entry, just like everywhere else.

As I said this is tricky situation, though artpec-8 is derivative of samsung, we can't confirm 
if future versions (> 9) will be samsung derivative. 

But this would be case for all such custom ASIC manufactured by samsung, so I would like to
understand how this will be handled? 

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Please let us know if this explanation addresses your concerns.
We'll update the commit message and cover letter accordingly.

Best regards,
Krzysztof