RE: [PATCH 00/16] Add support for the Axis ARTPEC-8 SoC

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From: Krzysztof Kozlowski <krzk@kernel.org>
Sent: Monday, July 21, 2025 12:10 PM
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SungMin Park [off-list ref]; Pankaj Dubey
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Subject: Re: [PATCH 00/16] Add support for the Axis ARTPEC-8 SoC

On 21/07/2025 06:50, SeonGu Kang wrote:

quoted

2025-07-10 (목), 09:07 +0200, Krzysztof Kozlowski:

quoted

On 10/07/2025 02:20, ksk4725@coasia.com wrote:

quoted

From: SeonGu Kang <redacted>

Add basic support for the Axis ARTPEC-8 SoC.
This SoC contains four Cortex-A53 CPUs and other several IPs.

Patches 1 to 10 provide the support for the clock controller, which
is similar to other Samsung SoCs.

You should explain here (and in DTS patches or the bindings) the
hardware, that this is Samsung SoC.

You could also explain the differences from Exynos and proposed
handling of patches (because this is odd)

Also, entire patchset has wrong and incomplete SoBs. Your SoB is
missing everywhere, others have wrong order.

Please read submitting patches first.

This Custom SoC is owned by the Axis (OEM) and manufactured by the
Samsung (ODM). It has standard Samsung specific IP blocks.

It is designed by Samsung. It is Samsung SoC.

Anyway, don't explain to me, but in your patchset.

Hi Krzysztof,

Thank you for your review comments on the ARTPEC-8 platform patches.
I'd like to add more context about the ARTPEC-8 SoC to help clarify its
relationship with Exynos.

Here are the key details about ARTPEC-8:
   - Manufactured by Samsung Foundry
   - SoC architecture is owned by Axis Communications
	- On similar model as Tesla's FSD chip owned by Tesla and 
              manufactured and  by Samsung
   - IPs from both Samsung and Axis Communications

Samsung-provided IPs:
  - UART
  - Ethernet (Vendor: Synopsys)
       - Same IP has been integrated as integrated in FSD Chip
  - SDIO
  - SPI
  - HSI2C
  - I2S
  - CMU (Clock Management Unit)
       Follows same CMU HW architecture as Exynos SoC have
  - Pinctrl (GPIO)
  - PCIe (Vendor: Synopsys)
       Though Exynos, FSD, ARTPEC have same DesignWare Controller, 
       the glue/wrapper layer around DWC Core has differences across
       these SoCs. All manufactured by Samsung, but differences are there
       in HW design and for different products. For the same reason PCIe patch
       refactoring effort is being put by us [1] to streamline single Exynos driver
       which can support all Samsung manufactured SoCs having DWC PCIe controller.
      [1]: https://patchwork.ozlabs.org/project/linux-pci/patch/20250625165229.3458-2-shradha.t@samsung.com/

Axis-provided IPs:
    - VIP (Image Sensor Processing IP)
    - VPP (Video Post Processing)
    - GPU
    - CDC (Video Encoder)

As part of the upstreaming effort, Samsung and Coasia (DSP) team will work together
to upstream basic SoC support and Samsung IPs support.
The Axis team will be the primary maintainer for the ARTPEC-8 SoC codebase.

Given that ARTPEC-8 is a distinct SoC with its own set of IPs, we believe it's reasonable
to create a separate directory for it, similar to FSD.

We will remove Samsung and Coasia teams from the maintainers list in v2 and only
Axis team will be maintainer.

Maintainer list for previous generation of Axis chips (ARM based) is already present,
so this will be merged into that.

Please let us know if this explanation addresses your concerns. 
We'll update the commit message and cover letter accordingly.

Thanks,
Pankaj Dubey

Best regards,
Krzysztof