Re: [PATCH v1 2/3] arm64: dts: qcom: x1e80100: add bus topology for PCIe domain 3
From: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Date: 2025-03-20 22:06:34
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linux-arm-msm, linux-devicetree, lkml
On 20/03/2025 05:55, Wenbin Yao wrote:
quoted hunk ↗ jump to hunk
From: Qiang Yu <redacted> Add pcie3port node to represent the PCIe bridge of PCIe3 so that PCI slot voltage rails can be described under this node in the board's dts. Signed-off-by: Qiang Yu <redacted> Signed-off-by: Wenbin Yao <redacted> --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 46b79fce9..32e8d400a 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi@@ -3287,6 +3287,16 @@ opp-128000000 { opp-peak-kBps = <15753000 1>; }; }; + pcie3port: pcie@0 {
Missing newline, please check your dtb checks.
+ device_type = "pci"; + compatible = "pciclass,0604"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; };
Why is pice3port the only port to be enabled ? What about the other ports ?
pcie3_phy: phy@1be0000 {
--
2.34.1
--- bod