[PATCH v1 2/3] arm64: dts: qcom: x1e80100: add bus topology for PCIe domain 3
From: Wenbin Yao <hidden>
Date: 2025-03-20 05:55:26
Also in:
linux-arm-msm, linux-devicetree, lkml
Subsystem:
arm/qualcomm mailing list, arm/qualcomm support, the rest · Maintainers:
Bjorn Andersson, Konrad Dybcio, Linus Torvalds
From: Qiang Yu <redacted> Add pcie3port node to represent the PCIe bridge of PCIe3 so that PCI slot voltage rails can be described under this node in the board's dts. Signed-off-by: Qiang Yu <redacted> Signed-off-by: Wenbin Yao <redacted> --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 46b79fce9..32e8d400a 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi@@ -3287,6 +3287,16 @@ opp-128000000 { opp-peak-kBps = <15753000 1>; }; }; + pcie3port: pcie@0 { + device_type = "pci"; + compatible = "pciclass,0604"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie3_phy: phy@1be0000 {
--
2.34.1