On 2/24/25 01:48, Dmitry Baryshkov wrote:
On Sun, Feb 23, 2025 at 02:22:25PM +0200, Ivaylo Ivanov wrote:
quoted
Some SoCs don't provide explicit reset lines, so make them optional.
Is there an external reset or some other signal?
Well.. There probably are on a hardware level, but there's no interface
that exposes them to the kernel.. as far as I've seen. Resets are usually
managed via the blocks' registers. I can't say with certainty because I
don't have access to TRMs.
I can reword this commit message to make that clear.
Best regards,
Ivaylo
quoted
Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
---
drivers/phy/phy-snps-eusb2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Dmitry Baryshkov <redacted>