Hi, Sunyeal,
I quickly skimmed over the series and I fail to see where/how the HW
auto clock gating is enabled/configured. Would you please add more
details on how this works?
On 7/22/24 11:33 PM, Sunyeal Hong wrote:
quoted hunk ↗ jump to hunk
Add cmu_top, cmu_peric0 clock nodes and
switch USI clocks instead of dummy fixed-rate-clock.
Signed-off-by: Sunyeal Hong <redacted>
---
.../arm64/boot/dts/exynos/exynosautov920.dtsi | 40 +++++++++++++------
1 file changed, 27 insertions(+), 13 deletions(-)
diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
index c1c8566d74f5..54fc32074379 100644
--- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
cut
quoted hunk ↗ jump to hunk
@@ -224,7 +237,8 @@ serial_0: serial@10880000 {
interrupts = <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&uart0_bus>;
- clocks = <&clock_usi>, <&clock_usi>;
+ clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
isn't this MUX common to multiple GATEs? Wouldn't turning it off affect
other users than the serial?
Thanks,
ta
+ <&cmu_peric0 CLK_DOUT_PERIC0_USI00_USI>;
clock-names = "uart", "clk_uart_baud0";
samsung,uart-fifosize = <256>;
status = "disabled";