On 07/06/2024 10:52, Julien Stephan wrote:

Le ven. 12 janv. 2024 à 08:32, Krzysztof Kozlowski
[off-list ref] a écrit :

quoted

On 10/01/2024 15:14, Julien Stephan wrote:

quoted

From: Louis Kuo <redacted>

This adds the bindings, for the mediatek ISP3.0 SENINF module embedded in
some Mediatek SoC, such as the mt8365

...

quoted

+  clock-names:
+    items:
+      - const: camsys
+      - const: top_mux
+
+  phys:
+    minItems: 1
+    maxItems: 4
+    description:
+      phandle to the PHYs connected to CSI0/A, CSI1, CSI2 and CSI0B
+
+  phy-names:
+    minItems: 1
+    items:
+      - const: csi0
+      - const: csi1
+      - const: csi2
+      - const: csi0b

Why one hardware has flexible number of phys?

Hi Krzysztof,

seninf can have multiple port depending on the soc, each requiring its own phy

So it is fixed per soc? Then make it fixed per soc.

Best regards,
Krzysztof


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