On 14/09/2023 17:26, Geert Uytterhoeven wrote:
Hi Rob,
On Tue, Sep 12, 2023 at 6:03 PM Rob Herring [off-list ref] wrote:
quoted
On Tue, Sep 12, 2023 at 07:51:41AM +0300, Claudiu wrote:
quoted
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Add RZ/G3S (R9A08G045) Clock Pulse Generator (CPG) core clocks, module
clocks and resets.
This is part of the binding, so it can be squashed with the previous
patch. The ack there still stands.
Usually we keep it as a separate patch, to be queued in an immutable
branch, as it is included by both the clock driver and by DTS, but
not by the yaml bindings file.
Binding also should be shared, so you get compatible documented in both
places (thus lack of checkpatch warnings). It still should be one patch.
Best regards,
Krzysztof
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