Thread (50 messages) 50 messages, 9 authors, 2023-03-20

Re: [PATCH 04/12] soc: sifive: ccache: Add non-coherent DMA handling

From: Conor Dooley <conor.dooley@microchip.com>
Date: 2023-02-20 11:44:34
Also in: linux-devicetree, linux-riscv, lkml, netdev

On Sun, Feb 19, 2023 at 10:32:52PM +0100, Emil Renner Berthing wrote:
On Thu, 16 Feb 2023 at 19:51, Conor Dooley [off-list ref] wrote:
quoted
Emil,

+CC Daire

On Sat, Feb 11, 2023 at 05:18:13AM +0200, Cristian Ciocaltea wrote:
quoted
From: Emil Renner Berthing <kernel@esmil.dk>

Add functions to flush the caches and handle non-coherent DMA.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
[replace <asm/cacheflush.h> with <linux/cacheflush.h>]
Signed-off-by: Cristian Ciocaltea <redacted>
---
quoted
+void *sifive_ccache_set_uncached(void *addr, size_t size)
+{
+     phys_addr_t phys_addr = __pa(addr) + uncached_offset;
+     void *mem_base;
+
+     mem_base = memremap(phys_addr, size, MEMREMAP_WT);
+     if (!mem_base) {
+             pr_err("%s memremap failed for addr %p\n", __func__, addr);
+             return ERR_PTR(-EINVAL);
+     }
+
+     return mem_base;
+}
The rest of this I either get b/c we did it, or will become moot so I
amn't worried about it, but can you please explain this, in particular
the memremap that you're doing here?
No, I can't really. As we talked about it's also based on a prototype
by Atish. I'm sure you know that the general idea is that we want to
return a pointer that accesses the same physical memory, but through
the uncached alias.
Yah, I follow all the rest of what's going on - it's just this bit of it
that I don't.
I can't tell you exactly why it's done this way
though, sorry.
I had a bit of a look on lore, but don't really see anything there that
contained any discussion of what was going on here.

Adding Atish in the off-chance that he remembers!
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