On Tue, Feb 14, 2023 at 08:06:49PM +0200, Cristian Ciocaltea wrote:

On 2/13/23 10:30, Ben Dooks wrote:

quoted

On 11/02/2023 03:18, Cristian Ciocaltea wrote:

quoted

From: Emil Renner Berthing <kernel@esmil.dk>

quoted

quoted

diff --git a/arch/riscv/mm/dma-noncoherent.c

b/arch/riscv/mm/dma-noncoherent.c
index d919efab6eba..e07e53aea537 100644

--- a/arch/riscv/mm/dma-noncoherent.c
+++ b/arch/riscv/mm/dma-noncoherent.c

@@ -9,14 +9,21 @@

  #include <linux/dma-map-ops.h>
  #include <linux/mm.h>
  #include <asm/cacheflush.h>
+#include <soc/sifive/sifive_ccache.h>
  static bool noncoherent_supported;
  void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
                    enum dma_data_direction dir)
  {
-    void *vaddr = phys_to_virt(paddr);
+    void *vaddr;
+    if (sifive_ccache_handle_noncoherent()) {
+        sifive_ccache_flush_range(paddr, size);
+        return;
+    }
+
+    vaddr = phys_to_virt(paddr);
      switch (dir) {
      case DMA_TO_DEVICE:
          ALT_CMO_OP(clean, vaddr, size, riscv_cbom_block_size);

@@ -35,8 +42,14 @@ void arch_sync_dma_for_device(phys_addr_t paddr,

size_t size,
  void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
                 enum dma_data_direction dir)
  {
-    void *vaddr = phys_to_virt(paddr);
+    void *vaddr;
+
+    if (sifive_ccache_handle_noncoherent()) {
+        sifive_ccache_flush_range(paddr, size);
+        return;
+    }

ok, what happens if we have an system where the ccache and another level
of cache also requires maintenance operations?

TBH, I'd hope that a system with that complexity is also not trying to
manage the cache in this manner!

According to [1], the handling of non-coherent DMA on RISC-V is currently
being worked on, so I will respin the series as soon as the proper support
arrives.

But yeah, once that stuff lands we can carry out these operations only
for the platforms that need/"need" it.

Cheers,
Conor.